2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_CRU_RK3399_H_
8 #define __ASM_ARCH_CRU_RK3399_H_
12 /* Private data for the clock driver - used by rockchip_get_cru() */
13 struct rk3399_clk_priv {
14 struct rk3399_cru *cru;
17 struct rk3399_pmuclk_priv {
18 struct rk3399_pmucru *pmucru;
21 struct rk3399_pmucru {
25 u32 pmucru_clkfrac_con[2];
27 u32 pmucru_clkgate_con[3];
29 u32 pmucru_softrst_con[2];
31 u32 pmucru_rstnhold_con[2];
33 u32 pmucru_gatedis_con[2];
35 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
58 u32 glb_srst_fst_value;
59 u32 glb_srst_snd_value;
69 check_member(rk3399_cru, sdio1_con[1], 0x594);
72 #define OSC_HZ (24*MHz)
73 #define APLL_HZ (600*MHz)
74 #define GPLL_HZ (594*MHz)
75 #define CPLL_HZ (384*MHz)
76 #define PPLL_HZ (676*MHz)
78 #define PMU_PCLK_HZ (48*MHz)
80 #define ACLKM_CORE_HZ (300*MHz)
81 #define ATCLK_CORE_HZ (300*MHz)
82 #define PCLK_DBG_HZ (100*MHz)
84 #define PERIHP_ACLK_HZ (148500*KHz)
85 #define PERIHP_HCLK_HZ (148500*KHz)
86 #define PERIHP_PCLK_HZ (37125*KHz)
88 #define PERILP0_ACLK_HZ (99000*KHz)
89 #define PERILP0_HCLK_HZ (99000*KHz)
90 #define PERILP0_PCLK_HZ (49500*KHz)
92 #define PERILP1_HCLK_HZ (99000*KHz)
93 #define PERILP1_PCLK_HZ (49500*KHz)
95 #define PWM_CLOCK_HZ PMU_PCLK_HZ
97 enum apll_l_frequencies {
102 #endif /* __ASM_ARCH_CRU_RK3399_H_ */