1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
6 #ifndef __ASM_ARCH_CRU_RK3399_H_
7 #define __ASM_ARCH_CRU_RK3399_H_
11 /* Private data for the clock driver - used by rockchip_get_cru() */
12 struct rk3399_clk_priv {
13 struct rk3399_cru *cru;
16 struct rk3399_pmuclk_priv {
17 struct rk3399_pmucru *pmucru;
20 struct rk3399_pmucru {
24 u32 pmucru_clkfrac_con[2];
26 u32 pmucru_clkgate_con[3];
28 u32 pmucru_softrst_con[2];
30 u32 pmucru_rstnhold_con[2];
32 u32 pmucru_gatedis_con[2];
34 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
57 u32 glb_srst_fst_value;
58 u32 glb_srst_snd_value;
68 check_member(rk3399_cru, sdio1_con[1], 0x594);
71 #define OSC_HZ (24*MHz)
72 #define APLL_HZ (600*MHz)
73 #define GPLL_HZ (594*MHz)
74 #define CPLL_HZ (384*MHz)
75 #define PPLL_HZ (676*MHz)
77 #define PMU_PCLK_HZ (48*MHz)
79 #define ACLKM_CORE_HZ (300*MHz)
80 #define ATCLK_CORE_HZ (300*MHz)
81 #define PCLK_DBG_HZ (100*MHz)
83 #define PERIHP_ACLK_HZ (148500*KHz)
84 #define PERIHP_HCLK_HZ (148500*KHz)
85 #define PERIHP_PCLK_HZ (37125*KHz)
87 #define PERILP0_ACLK_HZ (99000*KHz)
88 #define PERILP0_HCLK_HZ (99000*KHz)
89 #define PERILP0_PCLK_HZ (49500*KHz)
91 #define PERILP1_HCLK_HZ (99000*KHz)
92 #define PERILP1_PCLK_HZ (49500*KHz)
94 #define PWM_CLOCK_HZ PMU_PCLK_HZ
96 enum apll_l_frequencies {
101 #endif /* __ASM_ARCH_CRU_RK3399_H_ */