2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_CRU_RK3399_H_
8 #define __ASM_ARCH_CRU_RK3399_H_
12 struct rk3399_pmucru {
16 u32 pmucru_clkfrac_con[2];
18 u32 pmucru_clkgate_con[3];
20 u32 pmucru_softrst_con[2];
22 u32 pmucru_rstnhold_con[2];
24 u32 pmucru_gatedis_con[2];
26 check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
49 u32 glb_srst_fst_value;
50 u32 glb_srst_snd_value;
60 check_member(rk3399_cru, sdio1_con[1], 0x594);
63 #define OSC_HZ (24*MHz)
64 #define APLL_HZ (600*MHz)
65 #define GPLL_HZ (594*MHz)
66 #define CPLL_HZ (384*MHz)
67 #define PPLL_HZ (594*MHz)
69 #define PMU_PCLK_HZ (99*MHz)
71 #define ACLKM_CORE_HZ (300*MHz)
72 #define ATCLK_CORE_HZ (300*MHz)
73 #define PCLK_DBG_HZ (100*MHz)
75 #define PERIHP_ACLK_HZ (148500*KHz)
76 #define PERIHP_HCLK_HZ (148500*KHz)
77 #define PERIHP_PCLK_HZ (37125*KHz)
79 #define PERILP0_ACLK_HZ (99000*KHz)
80 #define PERILP0_HCLK_HZ (99000*KHz)
81 #define PERILP0_PCLK_HZ (49500*KHz)
83 #define PERILP1_HCLK_HZ (99000*KHz)
84 #define PERILP1_PCLK_HZ (49500*KHz)
86 #define PWM_CLOCK_HZ PMU_PCLK_HZ
88 enum apll_l_frequencies {
93 #endif /* __ASM_ARCH_CRU_RK3399_H_ */