2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _ASM_ARCH_DDR_RK3288_H
8 #define _ASM_ARCH_DDR_RK3288_H
10 struct rk3288_ddr_pctl {
123 u32 dfitrrdlvlgateen;
142 u32 dfitrwrlvldelay0;
143 u32 dfitrwrlvldelay1;
144 u32 dfitrwrlvldelay2;
145 u32 dfitrrdlvldelay0;
146 u32 dfitrrdlvldelay1;
147 u32 dfitrrdlvldelay2;
148 u32 dfitrrdlvlgatedelay0;
149 u32 dfitrrdlvlgatedelay1;
150 u32 dfitrrdlvlgatedelay2;
156 check_member(rk3288_ddr_pctl, iptr, 0x03fc);
158 struct rk3288_ddr_publ_datx {
167 struct rk3288_ddr_publ {
203 struct rk3288_ddr_publ_datx datx8[4];
205 check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294);
218 check_member(rk3288_msch, devtodev, 0x003c);
221 #define DFI_INIT_START (1 << 0)
224 #define DFI_DRAM_CLK_SR_EN (1 << 0)
225 #define DFI_DRAM_CLK_DPD_EN (1 << 1)
228 #define DFI_PARITY_INTR_EN (1 << 0)
229 #define DFI_PARITY_EN (1 << 1)
232 #define TLP_RESP_TIME_SHIFT 16
233 #define LP_SR_EN (1 << 8)
234 #define LP_PD_EN (1 << 0)
236 /* PCT_DFITCTRLDELAY */
237 #define TCTRL_DELAY_TIME_SHIFT 0
239 /* PCT_DFITPHYWRDATA */
240 #define TPHY_WRDATA_TIME_SHIFT 0
242 /* PCT_DFITPHYRDLAT */
243 #define TPHY_RDLAT_TIME_SHIFT 0
245 /* PCT_DFITDRAMCLKDIS */
246 #define TDRAM_CLK_DIS_TIME_SHIFT 0
248 /* PCT_DFITDRAMCLKEN */
249 #define TDRAM_CLK_EN_TIME_SHIFT 0
252 #define RANK0_ODT_WRITE_SEL (1 << 3)
253 #define RANK1_ODT_WRITE_SEL (1 << 11)
255 /* PCTL_DFIODTCFG1 */
256 #define ODT_LEN_BL8_W_SHIFT 16
259 #define ACDLLCR_DLLDIS (1 << 31)
260 #define ACDLLCR_DLLSRST (1 << 30)
263 #define DXDLLCR_DLLDIS (1 << 31)
264 #define DXDLLCR_DLLSRST (1 << 30)
267 #define DLLGCR_SBIAS (1 << 30)
270 #define DQSRTT (1 << 9)
271 #define DQRTT (1 << 10)
274 #define PIR_INIT (1 << 0)
275 #define PIR_DLLSRST (1 << 1)
276 #define PIR_DLLLOCK (1 << 2)
277 #define PIR_ZCAL (1 << 3)
278 #define PIR_ITMSRST (1 << 4)
279 #define PIR_DRAMRST (1 << 5)
280 #define PIR_DRAMINIT (1 << 6)
281 #define PIR_QSTRN (1 << 7)
282 #define PIR_RVTRN (1 << 8)
283 #define PIR_ICPC (1 << 16)
284 #define PIR_DLLBYP (1 << 17)
285 #define PIR_CTLDINIT (1 << 18)
286 #define PIR_CLRSR (1 << 28)
287 #define PIR_LOCKBYP (1 << 29)
288 #define PIR_ZCALBYP (1 << 30)
289 #define PIR_INITBYP (1u << 31)
292 #define PGCR_DFTLMT_SHIFT 3
293 #define PGCR_DFTCMP_SHIFT 2
294 #define PGCR_DQSCFG_SHIFT 1
295 #define PGCR_ITMDMD_SHIFT 0
298 #define PGSR_IDONE (1 << 0)
299 #define PGSR_DLDONE (1 << 1)
300 #define PGSR_ZCDONE (1 << 2)
301 #define PGSR_DIDONE (1 << 3)
302 #define PGSR_DTDONE (1 << 4)
303 #define PGSR_DTERR (1 << 5)
304 #define PGSR_DTIERR (1 << 6)
305 #define PGSR_DFTERR (1 << 7)
306 #define PGSR_RVERR (1 << 8)
307 #define PGSR_RVEIRR (1 << 9)
310 #define PRT_ITMSRST_SHIFT 18
311 #define PRT_DLLLOCK_SHIFT 6
312 #define PRT_DLLSRST_SHIFT 0
315 #define PRT_DINIT0_SHIFT 0
316 #define PRT_DINIT1_SHIFT 19
319 #define PRT_DINIT2_SHIFT 0
320 #define PRT_DINIT3_SHIFT 17
323 #define DDRMD_LPDDR 0
327 #define DDRMD_LPDDR2_LPDDR3 4
329 #define DDRMD_SHIFT 0
334 #define DQSNRES_MASK 0xf
335 #define DQSNRES_SHIFT 8
336 #define DQSRES_MASK 0xf
337 #define DQSRES_SHIFT 4
340 #define TDQSCKMAX_SHIFT 27
341 #define TDQSCKMAX_MASK 7
342 #define TDQSCK_SHIFT 24
343 #define TDQSCK_MASK 7
346 #define DQSGX_SHIFT 5
348 #define DQSGE_SHIFT 8
355 #define SLEEP_STATE 3
356 #define WAKEUP_STATE 4
359 #define LP_TRIG_SHIFT 4
360 #define LP_TRIG_MASK 7
361 #define PCTL_STAT_MSK 7
368 #define LOW_POWER_ENTRY_REQ 6
369 #define LOW_POWER_EXIT_REQ 7
372 #define PD_OUTPUT_SHIFT 0
373 #define PU_OUTPUT_SHIFT 5
374 #define PD_ONDIE_SHIFT 10
375 #define PU_ONDIE_SHIFT 15
376 #define ZDEN_SHIFT 28
379 #define SBIAS_BYPASS (1 << 23)
382 #define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
383 #define PD_IDLE_SHIFT 8
384 #define MDDR_EN (2 << 22)
385 #define LPDDR2_EN (3 << 22)
386 #define DDR2_EN (0 << 5)
387 #define DDR3_EN (1 << 5)
388 #define LPDDR2_S2 (0 << 6)
389 #define LPDDR2_S4 (1 << 6)
390 #define MDDR_LPDDR2_BL_2 (0 << 20)
391 #define MDDR_LPDDR2_BL_4 (1 << 20)
392 #define MDDR_LPDDR2_BL_8 (2 << 20)
393 #define MDDR_LPDDR2_BL_16 (3 << 20)
394 #define DDR2_DDR3_BL_4 0
395 #define DDR2_DDR3_BL_8 1
396 #define TFAW_SHIFT 18
397 #define PD_EXIT_SLOW (0 << 17)
398 #define PD_EXIT_FAST (1 << 17)
399 #define PD_TYPE_SHIFT 16
400 #define BURSTLENGTH_SHIFT 20
403 #define POWER_UP_START (1 << 0)
406 #define POWER_UP_DONE (1 << 0)
421 #define LPDDR2_MA_SHIFT 4
422 #define LPDDR2_MA_MASK 0xff
423 #define LPDDR2_OP_SHIFT 12
424 #define LPDDR2_OP_MASK 0xff
426 #define START_CMD (1u << 31)
429 #define BUSWRTORD_SHIFT 4
430 #define BUSRDTOWR_SHIFT 2
431 #define BUSRDTORD_SHIFT 0
434 #define DDR3_DLL_DISABLE 1
437 *TODO(sjg@chromium.org): We use a PMU register to store SDRAM information for
438 * passing from SPL to U-Boot. It would probably be better to use a normal C
441 * sys_reg bitfield struct
448 * [23:22] cs0_row_ch1
449 * [21:20] cs1_row_ch1
462 #define SYS_REG_DDRTYPE_SHIFT 13
463 #define SYS_REG_DDRTYPE_MASK 7
464 #define SYS_REG_NUM_CH_SHIFT 12
465 #define SYS_REG_NUM_CH_MASK 1
466 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
467 #define SYS_REG_ROW_3_4_MASK 1
468 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
469 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
470 #define SYS_REG_RANK_MASK 1
471 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
472 #define SYS_REG_COL_MASK 3
473 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
474 #define SYS_REG_BK_MASK 1
475 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
476 #define SYS_REG_CS0_ROW_MASK 3
477 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
478 #define SYS_REG_CS1_ROW_MASK 3
479 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
480 #define SYS_REG_BW_MASK 3
481 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
482 #define SYS_REG_DBW_MASK 3