2 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef __ASM_ARCH_DDR_RK3368_H__
8 #define __ASM_ARCH_DDR_RK3368_H__
11 * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
12 * in a few details. Most notably, it has an additional field to track
13 * tREFI in controller cycles (i.e. trefi_mem_ddr3).
15 struct rk3368_ddr_pctl {
124 u32 dfitrrdlvlgateen;
143 u32 dfitrwrlvldelay0;
144 u32 dfitrwrlvldelay1;
145 u32 dfitrwrlvldelay2;
146 u32 dfitrrdlvldelay0;
147 u32 dfitrrdlvldelay1;
148 u32 dfitrrdlvldelay2;
149 u32 dfitrrdlvlgatedelay0;
150 u32 dfitrrdlvlgatedelay1;
151 u32 dfitrrdlvlgatedelay2;
157 check_member(rk3368_ddr_pctl, iptr, 0x03fc);
159 struct rk3368_ddrphy {
162 check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
175 check_member(rk3368_msch, devtodev, 0x003c);
179 NOC_RSP_ERR_STALL = BIT(9),
180 MOBILE_DDR_SEL = BIT(4),
181 DDR0_16BIT_EN = BIT(3),
182 MSCH0_MAINDDR3_DDR3 = BIT(2),
183 MSCH0_MAINPARTIALPOP = BIT(1),
184 UPCTL_C_ACTIVE = BIT(0),