2 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_GRF_RK3036_H
7 #define _ASM_ARCH_GRF_RK3036_H
12 unsigned int reserved[0x2a];
13 unsigned int gpio0a_iomux;
14 unsigned int gpio0b_iomux;
15 unsigned int gpio0c_iomux;
16 unsigned int gpio0d_iomux;
18 unsigned int gpio1a_iomux;
19 unsigned int gpio1b_iomux;
20 unsigned int gpio1c_iomux;
21 unsigned int gpio1d_iomux;
23 unsigned int gpio2a_iomux;
24 unsigned int gpio2b_iomux;
25 unsigned int gpio2c_iomux;
26 unsigned int gpio2d_iomux;
28 unsigned int reserved2[0x0a];
30 unsigned int reserved3[0x05];
31 unsigned int gpio0l_pull;
32 unsigned int gpio0h_pull;
33 unsigned int gpio1l_pull;
34 unsigned int gpio1h_pull;
35 unsigned int gpio2l_pull;
36 unsigned int gpio2h_pull;
37 unsigned int reserved4[4];
38 unsigned int soc_con0;
39 unsigned int soc_con1;
40 unsigned int soc_con2;
41 unsigned int soc_status0;
42 unsigned int reserved5;
43 unsigned int soc_con3;
44 unsigned int reserved6;
45 unsigned int dmac_con0;
46 unsigned int dmac_con1;
47 unsigned int dmac_con2;
48 unsigned int reserved7[5];
49 unsigned int uoc0_con5;
50 unsigned int reserved8[4];
51 unsigned int uoc1_con4;
52 unsigned int uoc1_con5;
53 unsigned int reserved9;
54 unsigned int ddrc_stat;
55 unsigned int uoc_con6;
56 unsigned int soc_status1;
57 unsigned int cpu_con0;
58 unsigned int cpu_con1;
59 unsigned int cpu_con2;
60 unsigned int cpu_con3;
61 unsigned int reserved10;
62 unsigned int reserved11;
63 unsigned int cpu_status0;
64 unsigned int cpu_status1;
65 unsigned int os_reg[8];
66 unsigned int reserved12[6];
67 unsigned int dll_con[4];
68 unsigned int dll_status[4];
69 unsigned int dfi_wrnum;
70 unsigned int dfi_rdnum;
71 unsigned int dfi_actnum;
72 unsigned int dfi_timerval;
73 unsigned int nfi_fifo[4];
74 unsigned int reserved13[0x10];
75 unsigned int usbphy0_con[8];
76 unsigned int usbphy1_con[8];
77 unsigned int reserved14[0x10];
78 unsigned int chip_tag;
79 unsigned int sdmmc_det_cnt;
81 check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
83 /* GRF_GPIO0A_IOMUX */
86 GPIO0A3_MASK = 1 << GPIO0A3_SHIFT,
91 GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
96 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
102 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
108 /* GRF_GPIO0B_IOMUX */
111 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
117 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
123 GPIO0B4_MASK = 3 << GPIO0B4_SHIFT,
129 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
135 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
147 /* GRF_GPIO0C_IOMUX */
150 GPIO0C4_MASK = 1 << GPIO0C4_SHIFT,
155 GPIO0C3_MASK = 1 << GPIO0C3_SHIFT,
160 GPIO0C2_MASK = 1 << GPIO0C2_SHIFT,
165 GPIO0C1_MASK = 1 << GPIO0C1_SHIFT,
171 GPIO0C0_MASK = 1 << GPIO0C0_SHIFT,
176 /* GRF_GPIO0D_IOMUX */
179 GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
184 GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
189 GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
194 /* GRF_GPIO1A_IOMUX */
197 GPIO1A5_MASK = 1 << GPIO1A5_SHIFT,
202 GPIO1A4_MASK = 1 << GPIO1A4_SHIFT,
207 GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
212 GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
218 GPIO1A1_MASK = 1 << GPIO1A1_SHIFT,
223 GPIO1A0_MASK = 1 << GPIO1A0_SHIFT,
229 /* GRF_GPIO1B_IOMUX */
232 GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
237 GPIO1B3_MASK = 1 << GPIO1B3_SHIFT,
242 GPIO1B2_MASK = 1 << GPIO1B2_SHIFT,
247 GPIO1B1_MASK = 1 << GPIO1B1_SHIFT,
252 GPIO1B0_MASK = 1 << GPIO1B0_SHIFT,
257 /* GRF_GPIO1C_IOMUX */
260 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
266 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
272 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
278 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
284 GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
289 GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
294 /* GRF_GPIO1D_IOMUX */
297 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
304 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
311 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
318 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
325 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
332 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
339 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
346 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
353 /* GRF_GPIO2A_IOMUX */
356 GPIO2A7_MASK = 1 << GPIO2A7_SHIFT,
361 GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
366 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
373 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
379 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
385 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
391 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
397 /* GRF_GPIO2B_IOMUX */
400 GPIO2B7_MASK = 1 << GPIO2B7_SHIFT,
405 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
411 GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
416 GPIO2B4_MASK = 1 << GPIO2B4_SHIFT,
421 GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
426 /* GRF_GPIO2C_IOMUX */
429 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
432 GPIO2C7_TESTCLK_OUT1,
435 GPIO2C6_MASK = 1 << GPIO2C6_SHIFT,
440 GPIO2C5_MASK = 1 << GPIO2C5_SHIFT,
445 GPIO2C4_MASK = 1 << GPIO2C4_SHIFT,
450 GPIO2C3_MASK = 1 << GPIO2C3_SHIFT,
455 GPIO2C2_MASK = 1 << GPIO2C2_SHIFT,
460 GPIO2C1_MASK = 1 << GPIO2C1_SHIFT,
465 GPIO2C0_MASK = 1 << GPIO2C0_SHIFT,
470 /* GRF_GPIO2D_IOMUX */
473 GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
478 GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
483 GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
488 GPIO2D1_MASK = 1 << GPIO2D1_SHIFT,