2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_GRF_RK3128_H
7 #define _ASM_ARCH_GRF_RK3128_H
12 unsigned int reserved[0x2a];
13 unsigned int gpio0a_iomux;
14 unsigned int gpio0b_iomux;
15 unsigned int gpio0c_iomux;
16 unsigned int gpio0d_iomux;
17 unsigned int gpio1a_iomux;
18 unsigned int gpio1b_iomux;
19 unsigned int gpio1c_iomux;
20 unsigned int gpio1d_iomux;
21 unsigned int gpio2a_iomux;
22 unsigned int gpio2b_iomux;
23 unsigned int gpio2c_iomux;
24 unsigned int gpio2d_iomux;
25 unsigned int gpio3a_iomux;
26 unsigned int gpio3b_iomux;
27 unsigned int gpio3c_iomux;
28 unsigned int gpio3d_iomux;
29 unsigned int gpio2c_iomux2;
30 unsigned int grf_cif_iomux;
31 unsigned int grf_cif_iomux1;
32 unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
33 unsigned int gpio0l_pull;
34 unsigned int gpio0h_pull;
35 unsigned int gpio1l_pull;
36 unsigned int gpio1h_pull;
37 unsigned int gpio2l_pull;
38 unsigned int gpio2h_pull;
39 unsigned int gpio3l_pull;
40 unsigned int gpio3h_pull;
41 unsigned int reserved2;
42 unsigned int soc_con0;
43 unsigned int soc_con1;
44 unsigned int soc_con2;
45 unsigned int soc_status0;
46 unsigned int reserved3[6];
47 unsigned int mac_con0;
48 unsigned int mac_con1;
49 unsigned int reserved4[4];
50 unsigned int uoc0_con0;
51 unsigned int reserved5;
52 unsigned int uoc1_con1;
53 unsigned int uoc1_con2;
54 unsigned int uoc1_con3;
55 unsigned int uoc1_con4;
56 unsigned int uoc1_con5;
57 unsigned int reserved6;
58 unsigned int ddrc_stat;
59 unsigned int reserved9;
60 unsigned int soc_status1;
61 unsigned int cpu_con0;
62 unsigned int cpu_con1;
63 unsigned int cpu_con2;
64 unsigned int cpu_con3;
65 unsigned int reserved10;
66 unsigned int reserved11;
67 unsigned int cpu_status0;
68 unsigned int cpu_status1;
69 unsigned int os_reg[8];
70 unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
71 unsigned int usbphy0_con[8];
72 unsigned int usbphy1_con[8];
73 unsigned int uoc_status0;
74 unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
75 unsigned int chip_tag;
76 unsigned int sdmmc_det_cnt;
78 check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
81 unsigned int wakeup_cfg;
82 unsigned int pwrdn_con;
83 unsigned int pwrdn_st;
84 unsigned int idle_req;
86 unsigned int pwrmode_con;
87 unsigned int pwr_state;
89 unsigned int core_pwrdwn_cnt;
90 unsigned int core_pwrup_cnt;
92 unsigned int ddr_sref_st;
95 unsigned int sys_reg[4];
97 check_member(rk3128_pmu, int_st, 0x34);
99 /* GRF_GPIO0A_IOMUX */
102 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
107 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
112 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
117 GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
122 GPIO0A1_MASK = 1 << GPIO0A1_SHIFT,
127 GPIO0A0_MASK = 1 << GPIO0A0_SHIFT,
132 /* GRF_GPIO0B_IOMUX */
135 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
141 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
147 GPIO0B4_MASK = 1 << GPIO0B4_SHIFT,
152 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
169 /* GRF_GPIO0D_IOMUX */
172 GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
177 GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
182 GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
187 GPIO0D1_MASK = 1 << GPIO0D1_SHIFT,
192 GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
198 /* GRF_GPIO1A_IOMUX */
201 GPIO1A5_MASK = 3 << GPIO1A5_SHIFT,
207 GPIO1A4_MASK = 3 << GPIO1A4_SHIFT,
213 GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
218 GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
224 GPIO1A1_MASK = 3 << GPIO1A1_SHIFT,
234 GPIO1A0_SDMMC_CLKOUT,
239 /* GRF_GPIO1B_IOMUX */
242 GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
247 GPIO1B6_MASK = 1 << GPIO1B6_SHIFT,
252 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
258 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
264 GPIO1B0_MASK = 3 << GPIO1B0_SHIFT,
270 /* GRF_GPIO1C_IOMUX */
273 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
279 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
285 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
291 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
297 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
303 GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
308 GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
313 /* GRF_GPIO1D_IOMUX */
316 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
323 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
330 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
337 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
344 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
351 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
358 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
365 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
372 /* GRF_GPIO2A_IOMUX */
375 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
381 GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
386 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
392 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
399 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
405 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
411 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
417 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
423 /* GRF_GPIO2B_IOMUX */
426 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
433 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
440 GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
447 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
454 GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
461 GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
468 GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
475 GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
482 /* GRF_GPIO2C_IOMUX */
485 GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
492 GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
499 GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
506 GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
513 /* GRF_GPIO2D_IOMUX */
516 GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
519 GPIO2D6_GMAC_COL = 4,
522 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
524 GPIO2D1_GMAC_MDC = 3,
527 /* GRF_GPIO2C_IOMUX2 */
530 GPIO2C7_MASK = 7 << GPIO2C7_SHIFT,
532 GPIO2C7_GMAC_TXD3 = 4,
535 GPIO2C6_MASK = 7 << GPIO2C6_SHIFT,
537 GPIO2C6_GMAC_TXD2 = 4,
540 GPIO2C5_MASK = 7 << GPIO2C5_SHIFT,
542 GPIO2C5_I2C2_SCL = 3,
546 GPIO2C4_MASK = 7 << GPIO2C4_SHIFT,
548 GPIO2C4_I2C2_SDA = 3,