2 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _ASM_ARCH_GRF_RK3188_H
8 #define _ASM_ARCH_GRF_RK3188_H
10 struct rk3188_grf_gpio_lh {
16 struct rk3188_grf_gpio_lh gpio_dir[4];
17 struct rk3188_grf_gpio_lh gpio_do[4];
18 struct rk3188_grf_gpio_lh gpio_en[4];
70 check_member(rk3188_grf, flash_cmd_p, 0x01a4);
72 /* GRF_GPIO0D_IOMUX */
98 GPIO0D3_EMMC_RSTN_OUT,
118 /* GRF_GPIO1A_IOMUX */
165 /* GRF_GPIO1B_IOMUX */
215 /* GRF_GPIO1D_IOMUX */
258 /* GRF_GPIO3A_IOMUX */
263 GPIO3A7_SDMMC0_DATA3,
268 GPIO3A6_SDMMC0_DATA2,
273 GPIO3A5_SDMMC0_DATA1,
278 GPIO3A4_SDMMC0_DATA0,
288 GPIO3A2_SDMMC0_CLKOUT,
293 GPIO3A1_SDMMC0_PWREN,
301 /* GRF_GPIO3B_IOMUX */
340 GPIO3B1_SDMMC0_WRITE_PRT,
345 GPIO3B0_SDMMC_DETECT_N,
348 /* GRF_GPIO3C_IOMUX */
353 GPIO3C7_SDMMC1_WRITE_PRT,
354 GPIO3C7_RMII_CRS_DVALID,
360 GPIO3C6_SDMMC1_DECTN,
367 GPIO3C5_SDMMC1_CLKOUT,
374 GPIO3C4_SDMMC1_DATA3,
381 GPIO3C3_SDMMC1_DATA2,
388 GPIO3C2_SDMMC1_DATA1,
395 GPIO3C1_SDMMC1_DATA0,
407 /* GRF_GPIO3D_IOMUX */
414 GPIO3D6_HOST_DRV_VBUS,
421 GPIO3D5_OTG_DRV_VBUS,
437 GPIO3D2_SDMMC1_INT_N,
442 GPIO3D1_SDMMC1_BACKEND_PWR,
448 GPIO3D0_SDMMC1_PWR_EN,
454 HSADC_CLK_DIR_SHIFT = 15,
455 HSADC_CLK_DIR_MASK = 1,
457 HSADC_SEL_SHIFT = 14,
460 NOC_REMAP_SHIFT = 12,
463 EMMC_FLASH_SEL_SHIFT = 11,
464 EMMC_FLASH_SEL_MASK = 1,
466 TZPC_REVISION_SHIFT = 7,
467 TZPC_REVISION_MASK = 0xf,
469 L2CACHE_ACC_SHIFT = 5,
470 L2CACHE_ACC_MASK = 3,
475 IMEMRD_WAIT_SHIFT = 1,
476 IMEMRD_WAIT_MASK = 3,
481 RKI2C4_SEL_SHIFT = 15,
484 RKI2C3_SEL_SHIFT = 14,
487 RKI2C2_SEL_SHIFT = 13,
490 RKI2C1_SEL_SHIFT = 12,
493 RKI2C0_SEL_SHIFT = 11,
496 VCODEC_SEL_SHIFT = 10,
499 PERI_EMEM_PAUSE_SHIFT = 9,
500 PERI_EMEM_PAUSE_MASK = 1,
502 PERI_USB_PAUSE_SHIFT = 8,
503 PERI_USB_PAUSE_MASK = 1,
505 SMC_MUX_MODE_0_SHIFT = 6,
506 SMC_MUX_MODE_0_MASK = 1,
508 SMC_SRAM_MW_0_SHIFT = 4,
509 SMC_SRAM_MW_0_MASK = 3,
511 SMC_REMAP_0_SHIFT = 3,
512 SMC_REMAP_0_MASK = 1,
514 SMC_A_GT_M0_SYNC_SHIFT = 2,
515 SMC_A_GT_M0_SYNC_MASK = 1,
517 EMAC_SPEED_SHIFT = 1,
526 SDIO_CLK_OUT_SR_SHIFT = 15,
527 SDIO_CLK_OUT_SR_MASK = 1,
529 MEM_EMA_L2C_SHIFT = 11,
530 MEM_EMA_L2C_MASK = 7,
532 MEM_EMA_A9_SHIFT = 8,
535 MSCH4_MAINDDR3_SHIFT = 7,
536 MSCH4_MAINDDR3_MASK = 1,
537 MSCH4_MAINDDR3_DDR3 = 1,
539 EMAC_NEWRCV_EN_SHIFT = 6,
540 EMAC_NEWRCV_EN_MASK = 1,
542 SW_ADDR15_EN_SHIFT = 5,
543 SW_ADDR15_EN_MASK = 1,
545 SW_ADDR16_EN_SHIFT = 4,
546 SW_ADDR16_EN_MASK = 1,
548 SW_ADDR17_EN_SHIFT = 3,
549 SW_ADDR17_EN_MASK = 1,
551 BANK2_TO_RANK_EN_SHIFT = 2,
552 BANK2_TO_RANK_EN_MASK = 1,
554 RANK_TO_ROW15_EN_SHIFT = 1,
555 RANK_TO_ROW15_EN_MASK = 1,
557 UPCTL_C_ACTIVE_IN_SHIFT = 0,
558 UPCTL_C_ACTIVE_IN_MASK = 1,
559 UPCTL_C_ACTIVE_IN_MAY = 0,
560 UPCTL_C_ACTIVE_IN_WILL,
565 DDR_16BIT_EN_SHIFT = 15,
566 DDR_16BIT_EN_MASK = 1,