2 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _ASM_ARCH_GRF_RK3188_H
8 #define _ASM_ARCH_GRF_RK3188_H
10 struct rk3188_grf_gpio_lh {
16 struct rk3188_grf_gpio_lh gpio_dir[4];
17 struct rk3188_grf_gpio_lh gpio_do[4];
18 struct rk3188_grf_gpio_lh gpio_en[4];
70 check_member(rk3188_grf, flash_cmd_p, 0x01a4);
74 HSADC_CLK_DIR_SHIFT = 15,
75 HSADC_CLK_DIR_MASK = 1,
83 EMMC_FLASH_SEL_SHIFT = 11,
84 EMMC_FLASH_SEL_MASK = 1,
86 TZPC_REVISION_SHIFT = 7,
87 TZPC_REVISION_MASK = 0xf,
89 L2CACHE_ACC_SHIFT = 5,
95 IMEMRD_WAIT_SHIFT = 1,
101 RKI2C4_SEL_SHIFT = 15,
104 RKI2C3_SEL_SHIFT = 14,
107 RKI2C2_SEL_SHIFT = 13,
110 RKI2C1_SEL_SHIFT = 12,
113 RKI2C0_SEL_SHIFT = 11,
116 VCODEC_SEL_SHIFT = 10,
119 PERI_EMEM_PAUSE_SHIFT = 9,
120 PERI_EMEM_PAUSE_MASK = 1,
122 PERI_USB_PAUSE_SHIFT = 8,
123 PERI_USB_PAUSE_MASK = 1,
125 SMC_MUX_MODE_0_SHIFT = 6,
126 SMC_MUX_MODE_0_MASK = 1,
128 SMC_SRAM_MW_0_SHIFT = 4,
129 SMC_SRAM_MW_0_MASK = 3,
131 SMC_REMAP_0_SHIFT = 3,
132 SMC_REMAP_0_MASK = 1,
134 SMC_A_GT_M0_SYNC_SHIFT = 2,
135 SMC_A_GT_M0_SYNC_MASK = 1,
137 EMAC_SPEED_SHIFT = 1,
146 SDIO_CLK_OUT_SR_SHIFT = 15,
147 SDIO_CLK_OUT_SR_MASK = 1,
149 MEM_EMA_L2C_SHIFT = 11,
150 MEM_EMA_L2C_MASK = 7,
152 MEM_EMA_A9_SHIFT = 8,
155 MSCH4_MAINDDR3_SHIFT = 7,
156 MSCH4_MAINDDR3_MASK = 1,
157 MSCH4_MAINDDR3_DDR3 = 1,
159 EMAC_NEWRCV_EN_SHIFT = 6,
160 EMAC_NEWRCV_EN_MASK = 1,
162 SW_ADDR15_EN_SHIFT = 5,
163 SW_ADDR15_EN_MASK = 1,
165 SW_ADDR16_EN_SHIFT = 4,
166 SW_ADDR16_EN_MASK = 1,
168 SW_ADDR17_EN_SHIFT = 3,
169 SW_ADDR17_EN_MASK = 1,
171 BANK2_TO_RANK_EN_SHIFT = 2,
172 BANK2_TO_RANK_EN_MASK = 1,
174 RANK_TO_ROW15_EN_SHIFT = 1,
175 RANK_TO_ROW15_EN_MASK = 1,
177 UPCTL_C_ACTIVE_IN_SHIFT = 0,
178 UPCTL_C_ACTIVE_IN_MASK = 1,
179 UPCTL_C_ACTIVE_IN_MAY = 0,
180 UPCTL_C_ACTIVE_IN_WILL,
185 DDR_16BIT_EN_SHIFT = 15,
186 DDR_16BIT_EN_MASK = 1,