2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_GRF_RK322X_H
7 #define _ASM_ARCH_GRF_RK322X_H
12 unsigned int gpio0a_iomux;
13 unsigned int gpio0b_iomux;
14 unsigned int gpio0c_iomux;
15 unsigned int gpio0d_iomux;
17 unsigned int gpio1a_iomux;
18 unsigned int gpio1b_iomux;
19 unsigned int gpio1c_iomux;
20 unsigned int gpio1d_iomux;
22 unsigned int gpio2a_iomux;
23 unsigned int gpio2b_iomux;
24 unsigned int gpio2c_iomux;
25 unsigned int gpio2d_iomux;
27 unsigned int gpio3a_iomux;
28 unsigned int gpio3b_iomux;
29 unsigned int gpio3c_iomux;
30 unsigned int gpio3d_iomux;
32 unsigned int reserved1[4];
33 unsigned int con_iomux;
34 unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
35 unsigned int gpio0_p[4];
36 unsigned int gpio1_p[4];
37 unsigned int gpio2_p[4];
38 unsigned int gpio3_p[4];
39 unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
40 unsigned int gpio0_e[4];
41 unsigned int gpio1_e[4];
42 unsigned int gpio2_e[4];
43 unsigned int gpio3_e[4];
44 unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
45 unsigned int soc_con[7];
46 unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
47 unsigned int soc_status[3];
49 unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
50 unsigned int cpu_con[4];
51 unsigned int reserved7[4];
52 unsigned int cpu_status[2];
53 unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
54 unsigned int os_reg[8];
55 unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
56 unsigned int ddrc_stat;
58 check_member(rk322x_grf, ddrc_stat, 0x604);
61 unsigned int soc_con[11];
62 unsigned int busdmac_con[4];
65 /* GRF_GPIO0A_IOMUX */
68 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
74 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
80 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
86 GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
91 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
96 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
101 /* GRF_GPIO0B_IOMUX */
104 GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
109 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
115 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
121 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
127 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
138 /* GRF_GPIO0C_IOMUX */
141 GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
146 GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
152 /* GRF_GPIO0D_IOMUX */
155 GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
162 GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
167 GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
172 GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
177 /* GRF_GPIO1A_IOMUX */
185 /* GRF_GPIO1B_IOMUX */
188 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
193 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
198 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
204 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
210 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
216 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
222 /* GRF_GPIO1C_IOMUX */
225 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
228 GPIO1C7_EMMC_RSTNOUT,
231 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
238 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
244 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
250 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
256 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
262 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
267 GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
269 GPIO1C0_SDMMC_CLKOUT,
272 /* GRF_GPIO1D_IOMUX */
275 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
281 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
287 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
293 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
299 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
305 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
311 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
317 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
323 /* GRF_GPIO2A_IOMUX */
326 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
332 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
338 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
344 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
350 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
356 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
362 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
368 /* GRF_GPIO2B_IOMUX */
371 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
376 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
382 GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
387 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
392 GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
397 GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
402 GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
408 GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
411 GPIO2B0_MAC_SPEED_IOUT,
414 /* GRF_GPIO2C_IOMUX */
417 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
422 GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
427 GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
433 GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
439 GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
444 GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
449 GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
454 GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
459 /* GRF_GPIO2D_IOMUX */
462 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
472 /* GRF_GPIO3C_IOMUX */
475 GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
480 GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
485 GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
490 /* GRF_GPIO3D_IOMUX */
493 GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
500 CON_IOMUX_GMAC_SHIFT = 15,
501 CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT,
502 CON_IOMUX_UART1SEL_SHIFT = 11,
503 CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
504 CON_IOMUX_UART2SEL_SHIFT = 8,
505 CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
506 CON_IOMUX_UART2SEL_2 = 0,
507 CON_IOMUX_UART2SEL_21,
508 CON_IOMUX_EMMCSEL_SHIFT = 7,
509 CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
510 CON_IOMUX_PWM3SEL_SHIFT = 3,
511 CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
512 CON_IOMUX_PWM2SEL_SHIFT = 2,
513 CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
514 CON_IOMUX_PWM1SEL_SHIFT = 1,
515 CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
516 CON_IOMUX_PWM0SEL_SHIFT = 0,
517 CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,