2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_GRF_RK322X_H
7 #define _ASM_ARCH_GRF_RK322X_H
12 unsigned int gpio0a_iomux;
13 unsigned int gpio0b_iomux;
14 unsigned int gpio0c_iomux;
15 unsigned int gpio0d_iomux;
17 unsigned int gpio1a_iomux;
18 unsigned int gpio1b_iomux;
19 unsigned int gpio1c_iomux;
20 unsigned int gpio1d_iomux;
22 unsigned int gpio2a_iomux;
23 unsigned int gpio2b_iomux;
24 unsigned int gpio2c_iomux;
25 unsigned int gpio2d_iomux;
27 unsigned int gpio3a_iomux;
28 unsigned int gpio3b_iomux;
29 unsigned int gpio3c_iomux;
30 unsigned int gpio3d_iomux;
32 unsigned int reserved1[4];
33 unsigned int con_iomux;
34 unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
35 unsigned int gpio0_p[4];
36 unsigned int gpio1_p[4];
37 unsigned int gpio2_p[4];
38 unsigned int gpio3_p[4];
39 unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
40 unsigned int gpio0_e[4];
41 unsigned int gpio1_e[4];
42 unsigned int gpio2_e[4];
43 unsigned int gpio3_e[4];
44 unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
45 unsigned int soc_con[7];
46 unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
47 unsigned int soc_status[3];
49 unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
50 unsigned int cpu_con[4];
51 unsigned int reserved7[4];
52 unsigned int cpu_status[2];
53 unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
54 unsigned int os_reg[8];
55 unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
56 unsigned int ddrc_stat;
57 unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
58 unsigned int sig_detect_con[2];
59 unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
60 unsigned int sig_detect_status[2];
61 unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
62 unsigned int sig_detect_clr[2];
63 unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
64 unsigned int emmc_det;
65 unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
66 unsigned int host0_con[3];
67 unsigned int reserved15;
68 unsigned int host1_con[3];
69 unsigned int reserved16;
70 unsigned int host2_con[3];
71 unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
72 unsigned int usbphy0_con[27];
73 unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
74 unsigned int usbphy1_con[27];
75 unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
76 unsigned int otg_con0;
77 unsigned int uoc_status0;
78 unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
79 unsigned int mac_con[2];
80 unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
81 unsigned int macphy_con[4];
82 unsigned int macphy_status;
84 check_member(rk322x_grf, ddrc_stat, 0x604);
87 unsigned int soc_con[11];
88 unsigned int busdmac_con[4];
91 /* GRF_GPIO0A_IOMUX */
94 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
100 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
106 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
112 GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
117 GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
122 GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
127 /* GRF_GPIO0B_IOMUX */
130 GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
135 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
141 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
147 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
153 GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
164 /* GRF_GPIO0C_IOMUX */
167 GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
172 GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
178 /* GRF_GPIO0D_IOMUX */
181 GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
188 GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
193 GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
198 GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
203 /* GRF_GPIO1A_IOMUX */
211 /* GRF_GPIO1B_IOMUX */
214 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
219 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
224 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
230 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
236 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
242 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
248 /* GRF_GPIO1C_IOMUX */
251 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
254 GPIO1C7_EMMC_RSTNOUT,
257 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
264 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
270 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
276 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
282 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
288 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
293 GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
295 GPIO1C0_SDMMC_CLKOUT,
298 /* GRF_GPIO1D_IOMUX */
301 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
307 GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
313 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
319 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
325 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
331 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
337 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
343 GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
349 /* GRF_GPIO2A_IOMUX */
352 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
358 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
364 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
370 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
376 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
382 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
388 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
394 /* GRF_GPIO2B_IOMUX */
397 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
402 GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
408 GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
413 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
418 GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
423 GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
428 GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
434 GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
437 GPIO2B0_MAC_SPEED_IOUT,
440 /* GRF_GPIO2C_IOMUX */
443 GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
448 GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
453 GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
459 GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
465 GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
470 GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
475 GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
480 GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
485 /* GRF_GPIO2D_IOMUX */
488 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
498 /* GRF_GPIO3C_IOMUX */
501 GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
506 GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
511 GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
516 /* GRF_GPIO3D_IOMUX */
519 GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
526 CON_IOMUX_GMAC_SHIFT = 15,
527 CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT,
528 CON_IOMUX_UART1SEL_SHIFT = 11,
529 CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
530 CON_IOMUX_UART2SEL_SHIFT = 8,
531 CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
532 CON_IOMUX_UART2SEL_2 = 0,
533 CON_IOMUX_UART2SEL_21,
534 CON_IOMUX_EMMCSEL_SHIFT = 7,
535 CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
536 CON_IOMUX_PWM3SEL_SHIFT = 3,
537 CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
538 CON_IOMUX_PWM2SEL_SHIFT = 2,
539 CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
540 CON_IOMUX_PWM1SEL_SHIFT = 1,
541 CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
542 CON_IOMUX_PWM0SEL_SHIFT = 0,
543 CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
546 /* GRF_MACPHY_CON0 */
548 MACPHY_CFG_ENABLE_SHIFT = 0,
549 MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT,