2 * (C) Copyright 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
5 * SPDX-License-Identifier: GPL-2.0
8 #ifndef _ASM_ARCH_GRF_RK3288_H
9 #define _ASM_ARCH_GRF_RK3288_H
11 struct rk3288_grf_gpio_lh {
55 struct rk3288_grf_gpio_lh gpio_sr[8];
107 u32 reserved1[(0x20-0x18)/4];
109 u32 reserved2[(0x40-0x28)/4];
111 u32 reserved3[(0x50-0x4c)/4];
128 u32 reserved4[(0x100-0x90)/4];
130 u32 reserved5[(0x120-0x108)/4];
134 /* GRF_GPIO1D_IOMUX */
157 /* GRF_GPIO2C_IOMUX */
170 /* GRF_GPIO3A_IOMUX */
175 GPIO3A7_FLASH0_DATA7,
181 GPIO3A6_FLASH0_DATA6,
187 GPIO3A5_FLASH0_DATA5,
193 GPIO3A4_FLASH0_DATA4,
199 GPIO3A3_FLASH0_DATA3,
205 GPIO3A2_FLASH0_DATA2,
211 GPIO3A1_FLASH0_DATA1,
217 GPIO3A0_FLASH0_DATA0,
221 /* GRF_GPIO3B_IOMUX */
265 /* GRF_GPIO3C_IOMUX */
277 GPIO3C1_EMMC_RSTNOUT,
286 /* GRF_GPIO3DL_IOMUX */
291 GPIO3D3_FLASH1_DATA3,
299 GPIO3D2_FLASH1_DATA2,
307 GPIO3DL1_FLASH1_DATA1,
315 GPIO3D0_FLASH1_DATA0,
321 /* GRF_GPIO3HL_IOMUX */
326 GPIO3D7_FLASH1_DATA7,
334 GPIO3D6_FLASH1_DATA6,
342 GPIO3D5_FLASH1_DATA5,
350 GPIO3D4_FLASH1_DATA4,
353 GPIO3D4_SDIO1_DETECTN,
356 /* GRF_GPIO4AL_IOMUX */
390 /* GRF_GPIO4AH_IOMUX */
398 GPIO4A7_SDIO1_CLKOUT,
424 /* GRF_GPIO4BL_IOMUX */
443 /* GRF_GPIO4C_IOMUX */
468 GPIO4C3_UART0BT_RTSN,
473 GPIO4C2_UART0BT_CTSN,
478 GPIO4C1_UART0BT_SOUT,
486 /* GRF_GPIO5B_IOMUX */
493 GPIO5B7_UART4EXP_SIN,
500 GPIO5B6_UART4EXP_SOUT,
507 GPIO5B5_UART4EXP_RTSN,
514 GPIO5B4_UART4EXP_CTSN,
519 GPIO5B3_UART1BB_RTSN,
525 GPIO5B2_UART1BB_CTSN,
531 GPIO5B1_UART1BB_SOUT,
541 /* GRF_GPIO5C_IOMUX */
565 /* GRF_GPIO6B_IOMUX */
575 GPIO6B2_I2C1AUDIO_SCL,
580 GPIO6B1_I2C1AUDIO_SDA,
588 /* GRF_GPIO6C_IOMUX */
593 GPIO6C6_SDMMC0_DECTN,
603 GPIO6C4_SDMMC0_CLKOUT,
609 GPIO6C3_SDMMC0_DATA3,
615 GPIO6C2_SDMMC0_DATA2,
621 GPIO6C1_SDMMC0_DATA1,
627 GPIO6C0_SDMMC0_DATA0,
631 /* GRF_GPIO7A_IOMUX */
636 GPIO7A7_UART3GPS_SIN,
638 GPIO7A7_HSADCT1_DATA0,
653 /* GRF_GPIO7B_IOMUX */
658 GPIO7B7_ISP_SHUTTERTRIG,
664 GPIO7B6_ISP_PRELIGHTTRIG,
670 GPIO7B5_ISP_FLASHTRIGOUT,
676 GPIO7B4_ISP_SHUTTEREN,
682 GPIO7B3_USB_DRVVBUS1,
688 GPIO7B2_UART3GPS_RTSN,
689 GPIO7B2_USB_DRVVBUS0,
694 GPIO7B1_UART3GPS_CTSN,
701 GPIO7B0_UART3GPS_SOUT,
703 GPIO7B0_HSADCT1_DATA1,
706 /* GRF_GPIO7CL_IOMUX */
711 GPIO7C3_I2C5HDMI_SDA,
712 GPIO7C3_EDPHDMII2C_SDA,
727 GPIO7C0_ISP_FLASHTRIGIN,
728 GPIO7C0_EDPHDMI_CECINOUTT1,
731 /* GRF_GPIO7CH_IOMUX */
736 GPIO7C7_UART2DBG_SOUT,
737 GPIO7C7_UART2DBG_SIROUT,
739 GPIO7C7_EDPHDMI_CECINOUT,
744 GPIO7C6_UART2DBG_SIN,
745 GPIO7C6_UART2DBG_SIRIN,
751 GPIO7C4_I2C5HDMI_SCL,
752 GPIO7C4_EDPHDMII2C_SCL,
755 /* GRF_GPIO8A_IOMUX */
774 GPIO8A5_I2C2SENSOR_SCL,
780 GPIO8A4_I2C2SENSOR_SDA,
807 /* GRF_GPIO8B_IOMUX */
824 PAUSE_MMC_PERI_SHIFT = 0xf,
825 PAUSE_MMC_PERI_MASK = 1,
827 PAUSE_EMEM_PERI_SHIFT = 0xe,
828 PAUSE_EMEM_PERI_MASK = 1,
830 PAUSE_USB_PERI_SHIFT = 0xd,
831 PAUSE_USB_PERI_MASK = 1,
833 GRF_FORCE_JTAG_SHIFT = 0xc,
834 GRF_FORCE_JTAG_MASK = 1,
836 GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
837 GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
839 GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
840 GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
842 DDR1_16BIT_EN_SHIFT = 9,
843 DDR1_16BIT_EN_MASK = 1,
845 DDR0_16BIT_EN_SHIFT = 8,
846 DDR0_16BIT_EN_MASK = 1,
850 VCODEC_SELECT_VEPU_ACLK = 0,
851 VCODEC_SELECT_VDPU_ACLK,
853 UPCTL1_C_ACTIVE_IN_SHIFT = 6,
854 UPCTL1_C_ACTIVE_IN_MASK = 1,
855 UPCTL1_C_ACTIVE_IN_MAY = 0,
856 UPCTL1_C_ACTIVE_IN_WILL,
858 UPCTL0_C_ACTIVE_IN_SHIFT = 5,
859 UPCTL0_C_ACTIVE_IN_MASK = 1,
860 UPCTL0_C_ACTIVE_IN_MAY = 0,
861 UPCTL0_C_ACTIVE_IN_WILL,
863 MSCH1_MAINDDR3_SHIFT = 4,
864 MSCH1_MAINDDR3_MASK = 1,
865 MSCH1_MAINDDR3_DDR3 = 1,
867 MSCH0_MAINDDR3_SHIFT = 3,
868 MSCH0_MAINDDR3_MASK = 1,
869 MSCH0_MAINDDR3_DDR3 = 1,
871 MSCH1_MAINPARTIALPOP_SHIFT = 2,
872 MSCH1_MAINPARTIALPOP_MASK = 1,
874 MSCH0_MAINPARTIALPOP_SHIFT = 1,
875 MSCH0_MAINPARTIALPOP_MASK = 1,
880 RK3288_RMII_MODE_SHIFT = 14,
881 RK3288_RMII_MODE_MASK = (1 << RK3288_RMII_MODE_SHIFT),
882 RK3288_RMII_MODE = (1 << RK3288_RMII_MODE_SHIFT),
884 RK3288_GMAC_CLK_SEL_SHIFT = 12,
885 RK3288_GMAC_CLK_SEL_MASK = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
886 RK3288_GMAC_CLK_SEL_125M = (0 << RK3288_GMAC_CLK_SEL_SHIFT),
887 RK3288_GMAC_CLK_SEL_25M = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
888 RK3288_GMAC_CLK_SEL_2_5M = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
890 RK3288_RMII_CLK_SEL_SHIFT = 11,
891 RK3288_RMII_CLK_SEL_MASK = (1 << RK3288_RMII_CLK_SEL_SHIFT),
892 RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT),
893 RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT),
895 GMAC_SPEED_SHIFT = 0xa,
900 GMAC_FLOWCTRL_SHIFT = 0x9,
901 GMAC_FLOWCTRL_MASK = 1,
903 RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
904 RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
905 RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
906 RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
908 HOST_REMAP_SHIFT = 0x5,
914 UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
915 UPCTL1_LPDDR3_ODT_EN_MASK = 1,
916 UPCTL1_LPDDR3_ODT_EN_ODT = 1,
918 UPCTL1_BST_DIABLE_SHIFT = 0xc,
919 UPCTL1_BST_DIABLE_MASK = 1,
920 UPCTL1_BST_DIABLE_DISABLE = 1,
922 LPDDR3_EN1_SHIFT = 0xb,
924 LPDDR3_EN1_LPDDR3 = 1,
926 UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
927 UPCTL0_LPDDR3_ODT_EN_MASK = 1,
928 UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
930 UPCTL0_BST_DIABLE_SHIFT = 9,
931 UPCTL0_BST_DIABLE_MASK = 1,
932 UPCTL0_BST_DIABLE_DISABLE = 1,
934 LPDDR3_EN0_SHIFT = 8,
936 LPDDR3_EN0_LPDDR3 = 1,
938 GRF_POC_FLASH0_CTRL_SHIFT = 7,
939 GRF_POC_FLASH0_CTRL_MASK = 1,
940 GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
941 GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
943 SIMCARD_MUX_SHIFT = 6,
944 SIMCARD_MUX_MASK = 1,
945 SIMCARD_MUX_USE_A = 1,
946 SIMCARD_MUX_USE_B = 0,
948 GRF_SPDIF_2CH_EN_SHIFT = 1,
949 GRF_SPDIF_2CH_EN_MASK = 1,
950 GRF_SPDIF_2CH_EN_8CH = 0,
951 GRF_SPDIF_2CH_EN_2CH,
961 RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
962 RK3288_RXCLK_DLY_ENA_GMAC_MASK =
963 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
964 RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
965 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE =
966 (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
968 RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
969 RK3288_TXCLK_DLY_ENA_GMAC_MASK =
970 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
971 RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
972 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
973 (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
975 RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
976 RK3288_CLK_RX_DL_CFG_GMAC_MASK =
977 (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT),
979 RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
980 RK3288_CLK_TX_DL_CFG_GMAC_MASK =
981 (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT),
986 RK3288_HDMI_EDP_SEL_SHIFT = 0xf,
987 RK3288_HDMI_EDP_SEL_MASK =
988 1 << RK3288_HDMI_EDP_SEL_SHIFT,
989 RK3288_HDMI_EDP_SEL_EDP = 0,
990 RK3288_HDMI_EDP_SEL_HDMI,
992 RK3288_DSI0_DPICOLORM_SHIFT = 0x8,
993 RK3288_DSI0_DPICOLORM_MASK =
994 1 << RK3288_DSI0_DPICOLORM_SHIFT,
996 RK3288_DSI0_DPISHUTDN_SHIFT = 0x7,
997 RK3288_DSI0_DPISHUTDN_MASK =
998 1 << RK3288_DSI0_DPISHUTDN_SHIFT,
1000 RK3288_DSI0_LCDC_SEL_SHIFT = 0x6,
1001 RK3288_DSI0_LCDC_SEL_MASK =
1002 1 << RK3288_DSI0_LCDC_SEL_SHIFT,
1003 RK3288_DSI0_LCDC_SEL_BIG = 0,
1004 RK3288_DSI0_LCDC_SEL_LIT = 1,
1006 RK3288_EDP_LCDC_SEL_SHIFT = 0x5,
1007 RK3288_EDP_LCDC_SEL_MASK =
1008 1 << RK3288_EDP_LCDC_SEL_SHIFT,
1009 RK3288_EDP_LCDC_SEL_BIG = 0,
1010 RK3288_EDP_LCDC_SEL_LIT = 1,
1012 RK3288_HDMI_LCDC_SEL_SHIFT = 0x4,
1013 RK3288_HDMI_LCDC_SEL_MASK =
1014 1 << RK3288_HDMI_LCDC_SEL_SHIFT,
1015 RK3288_HDMI_LCDC_SEL_BIG = 0,
1016 RK3288_HDMI_LCDC_SEL_LIT = 1,
1018 RK3288_LVDS_LCDC_SEL_SHIFT = 0x3,
1019 RK3288_LVDS_LCDC_SEL_MASK =
1020 1 << RK3288_LVDS_LCDC_SEL_SHIFT,
1021 RK3288_LVDS_LCDC_SEL_BIG = 0,
1022 RK3288_LVDS_LCDC_SEL_LIT = 1,
1025 /* RK3288_SOC_CON8 */
1027 RK3288_DPHY_TX0_RXMODE_SHIFT = 4,
1028 RK3288_DPHY_TX0_RXMODE_MASK =
1029 0xf << RK3288_DPHY_TX0_RXMODE_SHIFT,
1030 RK3288_DPHY_TX0_RXMODE_EN = 0xf,
1031 RK3288_DPHY_TX0_RXMODE_DIS = 0,
1033 RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8,
1034 RK3288_DPHY_TX0_TXSTOPMODE_MASK =
1035 0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT,
1036 RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf,
1037 RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0,
1039 RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0,
1040 RK3288_DPHY_TX0_TURNREQUEST_MASK =
1041 0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT,
1042 RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf,
1043 RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
1046 /* GPIO Bias settings */
1054 #define GPIO_BIAS_MASK 0x3
1055 #define GPIO_BIAS_SHIFT(x) ((x) * 2)
1058 GPIO_PULL_NORMAL = 0,
1064 #define GPIO_PULL_MASK 0x3
1065 #define GPIO_PULL_SHIFT(x) ((x) * 2)