2 * (C) Copyright 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
5 * SPDX-License-Identifier: GPL-2.0
8 #ifndef _ASM_ARCH_GRF_RK3288_H
9 #define _ASM_ARCH_GRF_RK3288_H
11 struct rk3288_grf_gpio_lh {
55 struct rk3288_grf_gpio_lh gpio_sr[8];
107 u32 reserved1[(0x20-0x18)/4];
109 u32 reserved2[(0x40-0x28)/4];
111 u32 reserved3[(0x50-0x4c)/4];
128 u32 reserved4[(0x100-0x90)/4];
130 u32 reserved5[(0x120-0x108)/4];
134 /* GRF_GPIO1D_IOMUX */
157 /* GRF_GPIO2C_IOMUX */
170 /* GRF_GPIO3A_IOMUX */
175 GPIO3A7_FLASH0_DATA7,
181 GPIO3A6_FLASH0_DATA6,
187 GPIO3A5_FLASH0_DATA5,
193 GPIO3A4_FLASH0_DATA4,
199 GPIO3A3_FLASH0_DATA3,
205 GPIO3A2_FLASH0_DATA2,
211 GPIO3A1_FLASH0_DATA1,
217 GPIO3A0_FLASH0_DATA0,
221 /* GRF_GPIO3B_IOMUX */
265 /* GRF_GPIO3C_IOMUX */
277 GPIO3C1_EMMC_RSTNOUT,
286 /* GRF_GPIO4C_IOMUX */
311 GPIO4C3_UART0BT_RTSN,
316 GPIO4C2_UART0BT_CTSN,
321 GPIO4C1_UART0BT_SOUT,
329 /* GRF_GPIO5B_IOMUX */
336 GPIO5B7_UART4EXP_SIN,
343 GPIO5B6_UART4EXP_SOUT,
350 GPIO5B5_UART4EXP_RTSN,
357 GPIO5B4_UART4EXP_CTSN,
362 GPIO5B3_UART1BB_RTSN,
368 GPIO5B2_UART1BB_CTSN,
374 GPIO5B1_UART1BB_SOUT,
384 /* GRF_GPIO5C_IOMUX */
408 /* GRF_GPIO6B_IOMUX */
418 GPIO6B2_I2C1AUDIO_SCL,
423 GPIO6B1_I2C1AUDIO_SDA,
431 /* GRF_GPIO6C_IOMUX */
436 GPIO6C6_SDMMC0_DECTN,
446 GPIO6C4_SDMMC0_CLKOUT,
452 GPIO6C3_SDMMC0_DATA3,
458 GPIO6C2_SDMMC0_DATA2,
464 GPIO6C1_SDMMC0_DATA1,
470 GPIO6C0_SDMMC0_DATA0,
474 /* GRF_GPIO7A_IOMUX */
479 GPIO7A7_UART3GPS_SIN,
481 GPIO7A7_HSADCT1_DATA0,
496 /* GRF_GPIO7B_IOMUX */
501 GPIO7B7_ISP_SHUTTERTRIG,
507 GPIO7B6_ISP_PRELIGHTTRIG,
513 GPIO7B5_ISP_FLASHTRIGOUT,
519 GPIO7B4_ISP_SHUTTEREN,
525 GPIO7B3_USB_DRVVBUS1,
531 GPIO7B2_UART3GPS_RTSN,
532 GPIO7B2_USB_DRVVBUS0,
537 GPIO7B1_UART3GPS_CTSN,
544 GPIO7B0_UART3GPS_SOUT,
546 GPIO7B0_HSADCT1_DATA1,
549 /* GRF_GPIO7CL_IOMUX */
554 GPIO7C3_I2C5HDMI_SDA,
555 GPIO7C3_EDPHDMII2C_SDA,
570 GPIO7C0_ISP_FLASHTRIGIN,
571 GPIO7C0_EDPHDMI_CECINOUTT1,
574 /* GRF_GPIO7CH_IOMUX */
579 GPIO7C7_UART2DBG_SOUT,
580 GPIO7C7_UART2DBG_SIROUT,
582 GPIO7C7_EDPHDMI_CECINOUT,
587 GPIO7C6_UART2DBG_SIN,
588 GPIO7C6_UART2DBG_SIRIN,
594 GPIO7C4_I2C5HDMI_SCL,
595 GPIO7C4_EDPHDMII2C_SCL,
598 /* GRF_GPIO8A_IOMUX */
617 GPIO8A5_I2C2SENSOR_SCL,
623 GPIO8A4_I2C2SENSOR_SDA,
650 /* GRF_GPIO8B_IOMUX */
667 PAUSE_MMC_PERI_SHIFT = 0xf,
668 PAUSE_MMC_PERI_MASK = 1,
670 PAUSE_EMEM_PERI_SHIFT = 0xe,
671 PAUSE_EMEM_PERI_MASK = 1,
673 PAUSE_USB_PERI_SHIFT = 0xd,
674 PAUSE_USB_PERI_MASK = 1,
676 GRF_FORCE_JTAG_SHIFT = 0xc,
677 GRF_FORCE_JTAG_MASK = 1,
679 GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
680 GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
682 GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
683 GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
685 DDR1_16BIT_EN_SHIFT = 9,
686 DDR1_16BIT_EN_MASK = 1,
688 DDR0_16BIT_EN_SHIFT = 8,
689 DDR0_16BIT_EN_MASK = 1,
693 VCODEC_SELECT_VEPU_ACLK = 0,
694 VCODEC_SELECT_VDPU_ACLK,
696 UPCTL1_C_ACTIVE_IN_SHIFT = 6,
697 UPCTL1_C_ACTIVE_IN_MASK = 1,
698 UPCTL1_C_ACTIVE_IN_MAY = 0,
699 UPCTL1_C_ACTIVE_IN_WILL,
701 UPCTL0_C_ACTIVE_IN_SHIFT = 5,
702 UPCTL0_C_ACTIVE_IN_MASK = 1,
703 UPCTL0_C_ACTIVE_IN_MAY = 0,
704 UPCTL0_C_ACTIVE_IN_WILL,
706 MSCH1_MAINDDR3_SHIFT = 4,
707 MSCH1_MAINDDR3_MASK = 1,
708 MSCH1_MAINDDR3_DDR3 = 1,
710 MSCH0_MAINDDR3_SHIFT = 3,
711 MSCH0_MAINDDR3_MASK = 1,
712 MSCH0_MAINDDR3_DDR3 = 1,
714 MSCH1_MAINPARTIALPOP_SHIFT = 2,
715 MSCH1_MAINPARTIALPOP_MASK = 1,
717 MSCH0_MAINPARTIALPOP_SHIFT = 1,
718 MSCH0_MAINPARTIALPOP_MASK = 1,
723 RMII_MODE_SHIFT = 0xe,
727 GMAC_CLK_SEL_SHIFT = 0xc,
728 GMAC_CLK_SEL_MASK = 3,
729 GMAC_CLK_SEL_125M = 0,
730 GMAC_CLK_SEL_25M = 0x3,
731 GMAC_CLK_SEL_2_5M = 0x2,
733 RMII_CLK_SEL_SHIFT = 0xb,
734 RMII_CLK_SEL_MASK = 1,
735 RMII_CLK_SEL_2_5M = 0,
738 GMAC_SPEED_SHIFT = 0xa,
743 GMAC_FLOWCTRL_SHIFT = 0x9,
744 GMAC_FLOWCTRL_MASK = 1,
746 GMAC_PHY_INTF_SEL_SHIFT = 0x6,
747 GMAC_PHY_INTF_SEL_MASK = 0x7,
748 GMAC_PHY_INTF_SEL_RGMII = 0x1,
749 GMAC_PHY_INTF_SEL_RMII = 0x4,
751 HOST_REMAP_SHIFT = 0x5,
757 UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
758 UPCTL1_LPDDR3_ODT_EN_MASK = 1,
759 UPCTL1_LPDDR3_ODT_EN_ODT = 1,
761 UPCTL1_BST_DIABLE_SHIFT = 0xc,
762 UPCTL1_BST_DIABLE_MASK = 1,
763 UPCTL1_BST_DIABLE_DISABLE = 1,
765 LPDDR3_EN1_SHIFT = 0xb,
767 LPDDR3_EN1_LPDDR3 = 1,
769 UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
770 UPCTL0_LPDDR3_ODT_EN_MASK = 1,
771 UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
773 UPCTL0_BST_DIABLE_SHIFT = 9,
774 UPCTL0_BST_DIABLE_MASK = 1,
775 UPCTL0_BST_DIABLE_DISABLE = 1,
777 LPDDR3_EN0_SHIFT = 8,
779 LPDDR3_EN0_LPDDR3 = 1,
781 GRF_POC_FLASH0_CTRL_SHIFT = 7,
782 GRF_POC_FLASH0_CTRL_MASK = 1,
783 GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
784 GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
786 SIMCARD_MUX_SHIFT = 6,
787 SIMCARD_MUX_MASK = 1,
788 SIMCARD_MUX_USE_A = 1,
789 SIMCARD_MUX_USE_B = 0,
791 GRF_SPDIF_2CH_EN_SHIFT = 1,
792 GRF_SPDIF_2CH_EN_MASK = 1,
793 GRF_SPDIF_2CH_EN_8CH = 0,
794 GRF_SPDIF_2CH_EN_2CH,
804 RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
805 RXCLK_DLY_ENA_GMAC_MASK = 1,
806 RXCLK_DLY_ENA_GMAC_DISABLE = 0,
807 RXCLK_DLY_ENA_GMAC_ENABLE,
809 TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
810 TXCLK_DLY_ENA_GMAC_MASK = 1,
811 TXCLK_DLY_ENA_GMAC_DISABLE = 0,
812 TXCLK_DLY_ENA_GMAC_ENABLE,
814 CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
815 CLK_RX_DL_CFG_GMAC_MASK = 0x7f,
817 CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
818 CLK_TX_DL_CFG_GMAC_MASK = 0x7f,