2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __SOC_ROCKCHIP_RK3328_GRF_H__
8 #define __SOC_ROCKCHIP_RK3328_GRF_H__
10 struct rk3328_grf_regs {
32 u32 reserved1[(0x100 - 0x54) / 4];
50 u32 reserved2[(0x200 - 0x140) / 4];
67 u32 reserved3[(0x300 - 0x240) / 4];
76 u32 reserved4[(0x380 - 0x320) / 4];
85 u32 reserved5[(0x400 - 0x3a0) / 4];
87 u32 reserved6[(0x480 - 0x42c) / 4];
89 u32 reserved7[(0x4c0 - 0x494) / 4];
91 u32 reserved8[(0x500 - 0x4c8) / 4];
93 u32 reserved9[(0x520 - 0x508) / 4];
95 u32 reserved10[(0x5c8 - 0x528) / 4];
97 u32 reserved11[(0x680 - 0x5e8) / 4];
100 u32 sig_detect_status;
102 u32 sig_detect_status_clr;
105 u32 sdmmc_det_counter;
106 u32 reserved15[(0x700 - 0x6b4) / 4];
108 u32 reserved16[(0x880 - 0x70c) / 4];
112 u32 reserved18[(0x900 - 0x894) / 4];
114 u32 reserved19[(0xb00 - 0x90c) / 4];
118 check_member(rk3328_grf_regs, macphy_status, 0xb10);
120 struct rk3328_sgrf_regs {
122 u32 reserved0[(0x100 - 0x18) / 4];
124 u32 reserved1[(0x180 - 0x118) / 4];
126 u32 reserved2[(0x200 - 0x184) / 4];
128 u32 reserved3[(0x280 - 0x204) / 4];
130 u32 hdcp_key_access_mask;
132 check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
134 #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */