2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __SOC_ROCKCHIP_RK3328_GRF_H__
8 #define __SOC_ROCKCHIP_RK3328_GRF_H__
10 struct rk3328_grf_regs {
32 u32 reserved1[(0x100 - 0x54) / 4];
50 u32 reserved2[(0x200 - 0x140) / 4];
67 u32 reserved3[(0x300 - 0x240) / 4];
76 u32 reserved4[(0x380 - 0x320) / 4];
85 u32 reserved5[(0x400 - 0x3a0) / 4];
87 u32 reserved6[(0x480 - 0x42c) / 4];
89 u32 reserved7[(0x4c0 - 0x494) / 4];
91 u32 reserved8[(0x500 - 0x4c8) / 4];
93 u32 reserved9[(0x520 - 0x508) / 4];
95 u32 reserved10[(0x5c8 - 0x528) / 4];
97 u32 reserved11[(0x680 - 0x5e8) / 4];
100 u32 sig_detect_status;
102 u32 sig_detect_status_clr;
105 u32 sdmmc_det_counter;
106 u32 reserved15[(0x700 - 0x6b4) / 4];
108 u32 reserved16[(0x880 - 0x70c) / 4];
112 u32 reserved18[(0x900 - 0x894) / 4];
114 u32 reserved19[(0xb00 - 0x90c) / 4];
118 check_member(rk3328_grf_regs, macphy_status, 0xb10);
120 struct rk3328_sgrf_regs {
122 u32 reserved0[(0x100 - 0x18) / 4];
124 u32 reserved1[(0x180 - 0x118) / 4];
126 u32 reserved2[(0x200 - 0x184) / 4];
128 u32 reserved3[(0x280 - 0x204) / 4];
130 u32 hdcp_key_access_mask;
132 check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
136 GPIO0A5_SEL_SHIFT = 10,
137 GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
138 GPIO0A5_I2C3_SCL = 2,
140 GPIO0A6_SEL_SHIFT = 12,
141 GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
142 GPIO0A6_I2C3_SDA = 2,
144 GPIO0A7_SEL_SHIFT = 14,
145 GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
146 GPIO0A7_EMMC_DATA0 = 2,
149 GPIO0D6_SEL_SHIFT = 12,
150 GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
152 GPIO0D6_SDMMC0_PWRENM1 = 3,
155 GPIO1A0_SEL_SHIFT = 0,
156 GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
157 GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
160 GPIO2A0_SEL_SHIFT = 0,
161 GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
162 GPIO2A0_UART2_TX_M1 = 1,
164 GPIO2A1_SEL_SHIFT = 2,
165 GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
166 GPIO2A1_UART2_RX_M1 = 1,
168 GPIO2A2_SEL_SHIFT = 4,
169 GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
172 GPIO2A4_SEL_SHIFT = 8,
173 GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
177 GPIO2A5_SEL_SHIFT = 10,
178 GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
182 GPIO2A6_SEL_SHIFT = 12,
183 GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
186 GPIO2A7_SEL_SHIFT = 14,
187 GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
189 GPIO2A7_SDMMC0_PWRENM0,
192 GPIO2BL0_SEL_SHIFT = 0,
193 GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
194 GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
196 GPIO2BL3_SEL_SHIFT = 6,
197 GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
198 GPIO2BL3_SPI_CSN0_M0 = 1,
200 GPIO2BL4_SEL_SHIFT = 8,
201 GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
202 GPIO2BL4_SPI_CSN1_M0 = 1,
204 GPIO2BL5_SEL_SHIFT = 10,
205 GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
206 GPIO2BL5_I2C2_SDA = 1,
208 GPIO2BL6_SEL_SHIFT = 12,
209 GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
210 GPIO2BL6_I2C2_SCL = 1,
213 GPIO2D0_SEL_SHIFT = 0,
214 GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
215 GPIO2D0_I2C0_SCL = 1,
217 GPIO2D1_SEL_SHIFT = 2,
218 GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
219 GPIO2D1_I2C0_SDA = 1,
221 GPIO2D4_SEL_SHIFT = 8,
222 GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
223 GPIO2D4_EMMC_DATA1234 = 0xaa,
226 GPIO3C0_SEL_SHIFT = 0,
227 GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
228 GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
231 IOMUX_SEL_UART2_SHIFT = 0,
232 IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
233 IOMUX_SEL_UART2_M0 = 0,
236 IOMUX_SEL_SPI_SHIFT = 4,
237 IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
238 IOMUX_SEL_SPI_M0 = 0,
242 IOMUX_SEL_SDMMC_SHIFT = 7,
243 IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
244 IOMUX_SEL_SDMMC_M0 = 0,
248 #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */