1 /* (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 * SPDX-License-Identifier: GPL-2.0+
5 #ifndef _ASM_ARCH_GRF_RK3368_H
6 #define _ASM_ARCH_GRF_RK3368_H
78 check_member(rk3368_grf, soc_con17, 0x444);
80 struct rk3368_pmu_grf {
95 u32 reserved[(0x200 - 0x34) / 4 - 1];
98 check_member(rk3368_pmu_grf, os_reg[3], 0x20c);
103 GPIO0C7_MASK = 3 << GPIO0C7_SHIFT,
110 GPIO0C6_MASK = 3 << GPIO0C6_SHIFT,
117 GPIO0C5_MASK = 3 << GPIO0C5_SHIFT,
124 GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
131 GPIO0C3_MASK = 3 << GPIO0C3_SHIFT,
135 GPIO0C3_MCU_JTAG_TDO,
138 GPIO0C2_MASK = 3 << GPIO0C2_SHIFT,
142 GPIO0C2_MCU_JTAG_TDI,
145 GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
149 GPIO0C1_MCU_JTAG_TRTSN,
152 GPIO0C0_MASK = 3 << GPIO0C0_SHIFT,
156 GPIO0C0_MCU_JTAG_TDO,
162 GPIO0D7_MASK = 3 << GPIO0D7_SHIFT,
169 GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
176 GPIO0D5_MASK = 3 << GPIO0D5_SHIFT,
183 GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
190 GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
197 GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
204 GPIO0D1_MASK = 3 << GPIO0D1_SHIFT,
211 GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
221 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
227 GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
233 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
239 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
245 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
251 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
256 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
261 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
269 GPIO2D7_MASK = 3 << GPIO2D7_SHIFT,
274 GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
279 GPIO2D5_MASK = 3 << GPIO2D5_SHIFT,
284 GPIO2D4_MASK = 3 << GPIO2D4_SHIFT,
289 GPIO2D3_MASK = 3 << GPIO2D3_SHIFT,
294 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
299 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
304 GPIO2D0_MASK = 3 << GPIO2D0_SHIFT,
312 GPIO3C7_MASK = 3 << GPIO3C7_SHIFT,
314 GPIO3C7_EDPHDMI_CECINOUT,
315 GPIO3C7_ISP_FLASHTRIGIN,
318 GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
321 GPIO3C6_ISP_SHUTTERTRIG,
324 GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
327 GPIO3C5_ISP_PRELIGHTTRIG,
330 GPIO3C4_MASK = 3 << GPIO3C4_SHIFT,
333 GPIO3C4_ISP_FLASHTRIGOUT,
336 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
342 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
344 GPIO3C2_ISP_SHUTTEREN,
347 GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
353 GPIO3C0_MASK = 3 << GPIO3C0_SHIFT,
363 GPIO3D7_MASK = 3 << GPIO3D7_SHIFT,
370 GPIO3D6_MASK = 3 << GPIO3D6_SHIFT,
377 GPIO3D5_MASK = 3 << GPIO3D5_SHIFT,
383 GPIO3D4_MASK = 3 << GPIO3D4_SHIFT,
385 GPIO3D4_MAC_TXCLKOUT,
389 GPIO3D3_MASK = 3 << GPIO3D3_SHIFT,
395 GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
401 GPIO3D1_MASK = 3 << GPIO3D1_SHIFT,
407 GPIO3D0_MASK = 3 << GPIO3D0_SHIFT,
413 /*GRF_SOC_CON11/12/13*/
415 MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
416 MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
421 MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0,
422 MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
427 MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0,
428 MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
433 MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12,
434 MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
435 MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8,
436 MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
437 MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4,
438 MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
439 MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
440 MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),