1 /* (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 * SPDX-License-Identifier: GPL-2.0+
5 #ifndef _ASM_ARCH_GRF_RK3368_H
6 #define _ASM_ARCH_GRF_RK3368_H
78 check_member(rk3368_grf, soc_con17, 0x444);
80 struct rk3368_pmu_grf {
96 check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
101 GPIO0C7_MASK = 3 << GPIO0C7_SHIFT,
108 GPIO0C6_MASK = 3 << GPIO0C6_SHIFT,
115 GPIO0C5_MASK = 3 << GPIO0C5_SHIFT,
122 GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
129 GPIO0C3_MASK = 3 << GPIO0C3_SHIFT,
133 GPIO0C3_MCU_JTAG_TDO,
136 GPIO0C2_MASK = 3 << GPIO0C2_SHIFT,
140 GPIO0C2_MCU_JTAG_TDI,
143 GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
147 GPIO0C1_MCU_JTAG_TRTSN,
150 GPIO0C0_MASK = 3 << GPIO0C0_SHIFT,
154 GPIO0C0_MCU_JTAG_TDO,
160 GPIO0D7_MASK = 3 << GPIO0D7_SHIFT,
167 GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
174 GPIO0D5_MASK = 3 << GPIO0D5_SHIFT,
181 GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
188 GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
195 GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
202 GPIO0D1_MASK = 3 << GPIO0D1_SHIFT,
209 GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
219 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
225 GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
231 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
237 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
243 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
249 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
254 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
259 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
267 GPIO2D7_MASK = 3 << GPIO2D7_SHIFT,
272 GPIO2D6_MASK = 3 << GPIO2D6_SHIFT,
277 GPIO2D5_MASK = 3 << GPIO2D5_SHIFT,
282 GPIO2D4_MASK = 3 << GPIO2D4_SHIFT,
287 GPIO2D3_MASK = 3 << GPIO2D3_SHIFT,
292 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
297 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
302 GPIO2D0_MASK = 3 << GPIO2D0_SHIFT,
310 GPIO3C7_MASK = 3 << GPIO3C7_SHIFT,
312 GPIO3C7_EDPHDMI_CECINOUT,
313 GPIO3C7_ISP_FLASHTRIGIN,
316 GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
319 GPIO3C6_ISP_SHUTTERTRIG,
322 GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
325 GPIO3C5_ISP_PRELIGHTTRIG,
328 GPIO3C4_MASK = 3 << GPIO3C4_SHIFT,
331 GPIO3C4_ISP_FLASHTRIGOUT,
334 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
340 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
342 GPIO3C2_ISP_SHUTTEREN,
345 GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
351 GPIO3C0_MASK = 3 << GPIO3C0_SHIFT,
361 GPIO3D7_MASK = 3 << GPIO3D7_SHIFT,
368 GPIO3D6_MASK = 3 << GPIO3D6_SHIFT,
375 GPIO3D5_MASK = 3 << GPIO3D5_SHIFT,
381 GPIO3D4_MASK = 3 << GPIO3D4_SHIFT,
383 GPIO3D4_MAC_TXCLKOUT,
387 GPIO3D3_MASK = 3 << GPIO3D3_SHIFT,
393 GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
399 GPIO3D1_MASK = 3 << GPIO3D1_SHIFT,
405 GPIO3D0_MASK = 3 << GPIO3D0_SHIFT,
411 /*GRF_SOC_CON11/12/13*/
413 MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0,
414 MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
419 MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0,
420 MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
425 MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0,
426 MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0),
431 MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12,
432 MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12),
433 MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8,
434 MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8),
435 MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4,
436 MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4),
437 MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0,
438 MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0),