2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_GRF_RV1108_H
7 #define _ASM_ARCH_GRF_RV1108_H
113 check_member(rv1108_grf, chip_id, 0x0c00);
115 /* GRF_GPIO1B_IOMUX */
118 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
121 GPIO1B7_I2S_SDIO2_M0,
125 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
128 GPIO1B6_I2S_LRCLKTX_M0,
132 GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
135 GPIO1B5_I2S_SDIO1_M0,
139 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
146 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
153 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
160 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
172 /* GRF_GPIO1C_IOMUX */
175 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
178 GPIO1C7_I2S_SDIO2_M1,
181 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
184 GPIO1C6_I2S_LRCLKTX_M1,
187 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
193 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
199 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
205 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
208 GPIO1C2_I2S_SDIO3_M0,
212 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
222 GPIO1C0_I2S_LRCLKRX_M0,
225 /* GRF_GPIO1D_OIMUX */
228 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
234 GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
239 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
245 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
251 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
257 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
264 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
278 /* GRF_GPIO2A_IOMUX */
281 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
287 GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
293 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
299 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
305 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
309 GPIO2A3_SFC_HOLD_IO3,
312 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
319 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
326 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
333 /* GRF_GPIO2D_IOMUX */
336 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
342 GPIO2B6_MASK = 1 << GPIO2B6_SHIFT,
347 GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
352 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
359 GPIO2B3_MASK = 1 << GPIO2B3_SHIFT,
364 GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
369 GPIO2B1_MASK = 1 << GPIO2B1_SHIFT,
374 GPIO2B0_MASK = 1 << GPIO2B0_SHIFT,
379 /* GRF_GPIO2D_IOMUX */
382 GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
387 GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
392 GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
397 GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
402 GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
407 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
409 GPIO2D2_UART2_SOUT_M0,
413 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
415 GPIO2D1_UART2_SIN_M0,
427 /* GRF_GPIO3A_IOMUX */
430 GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
434 GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
439 GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
444 GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
449 GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
454 GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
459 GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
469 /* GRF_GPIO3C_IOMUX */
472 GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
477 GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
482 GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
487 GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
492 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
495 GPIO3C3_UART2_SOUT_M1,
498 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
501 GPIO3C2_UART2_SIN_M1,
504 GPIOC1_MASK = 1 << GPIOC1_SHIFT,