2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_GRF_RV1108_H
7 #define _ASM_ARCH_GRF_RV1108_H
109 check_member(rv1108_grf, chip_id, 0xf90);
111 /* GRF_GPIO1B_IOMUX */
114 GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
117 GPIO1B7_I2S_SDIO2_M0,
121 GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
124 GPIO1B6_I2S_LRCLKTX_M0,
128 GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
131 GPIO1B5_I2S_SDIO1_M0,
135 GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
142 GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
149 GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
156 GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
168 /* GRF_GPIO1C_IOMUX */
171 GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
174 GPIO1C7_I2S_SDIO2_M1,
177 GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
180 GPIO1C6_I2S_LRCLKTX_M1,
183 GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
189 GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
195 GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
201 GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
204 GPIO1C2_I2S_SDIO3_M0,
208 GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
218 GPIO1C0_I2S_LRCLKRX_M0,
221 /* GRF_GPIO1D_OIMUX */
224 GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
230 GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
235 GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
241 GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
247 GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
253 GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
260 GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
274 /* GRF_GPIO2A_IOMUX */
277 GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
283 GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
289 GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
295 GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
301 GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
305 GPIO2A3_SFC_HOLD_IO3,
308 GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
315 GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
322 GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
329 /* GRF_GPIO2D_IOMUX */
332 GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
338 GPIO2B6_MASK = 1 << GPIO2B6_SHIFT,
343 GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
348 GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
355 GPIO2B3_MASK = 1 << GPIO2B3_SHIFT,
360 GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
365 GPIO2B1_MASK = 1 << GPIO2B1_SHIFT,
370 GPIO2B0_MASK = 1 << GPIO2B0_SHIFT,
375 /* GRF_GPIO2D_IOMUX */
378 GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
383 GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
388 GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
393 GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
398 GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
403 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
405 GPIO2D2_UART2_SOUT_M0,
409 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
411 GPIO2D1_UART2_SIN_M0,
423 /* GRF_GPIO3A_IOMUX */
426 GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
430 GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
435 GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
440 GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
445 GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
450 GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
455 GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
465 /* GRF_GPIO3C_IOMUX */
468 GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
473 GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
478 GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
483 GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
488 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
491 GPIO3C3_UART2_SOUT_M1,
494 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
497 GPIO3C2_UART2_SIN_M1,
500 GPIOC1_MASK = 1 << GPIOC1_SHIFT,