git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-rockchip/pmu_rk3288.h

   1 /*
   2  * Copyright (c) 2015 Google, Inc
   3  *
   4  * Copyright 2014 Rockchip Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _ASM_ARCH_PMU_RK3288_H
  10 #define _ASM_ARCH_PMU_RK3288_H
  11
  12 struct rk3288_pmu {
  13         u32 wakeup_cfg[2];
  14         u32 pwrdn_con;
  15         u32 pwrdn_st;
  16
  17         u32 idle_req;
  18         u32 idle_st;
  19         u32 pwrmode_con;
  20         u32 pwr_state;
  21
  22         u32 osc_cnt;
  23         u32 pll_cnt;
  24         u32 stabl_cnt;
  25         u32 ddr0io_pwron_cnt;
  26
  27         u32 ddr1io_pwron_cnt;
  28         u32 core_pwrdn_cnt;
  29         u32 core_pwrup_cnt;
  30         u32 gpu_pwrdn_cnt;
  31
  32         u32 gpu_pwrup_cnt;
  33         u32 wakeup_rst_clr_cnt;
  34         u32 sft_con;
  35         u32 ddr_sref_st;
  36
  37         u32 int_con;
  38         u32 int_st;
  39         u32 boot_addr_sel;
  40         u32 grf_con;
  41
  42         u32 gpio_sr;
  43         u32 gpio0pull[3];
  44
  45         u32 gpio0drv[3];
  46         u32 gpio_op;
  47
  48         u32 gpio0_sel18;        /* 0x80 */
  49         u32 gpio0_iomux[4];     /* a, b, c, d */
  50         u32 sys_reg[4];
  51 };
  52 check_member(rk3288_pmu, sys_reg[3], 0x00a0);
  53
  54 enum {
  55         PMU_GPIO0_A     = 0,
  56         PMU_GPIO0_B,
  57         PMU_GPIO0_C,
  58         PMU_GPIO0_D,
  59 };
  60
  61 /* PMU_GPIO0_B_IOMUX */
  62 enum {
  63         GPIO0_B7_SHIFT          = 14,
  64         GPIO0_B7_MASK           = 1,
  65         GPIO0_B7_GPIOB7         = 0,
  66         GPIO0_B7_I2C0PMU_SDA,
  67
  68         GPIO0_B5_SHIFT          = 10,
  69         GPIO0_B5_MASK           = 1,
  70         GPIO0_B5_GPIOB5         = 0,
  71         GPIO0_B5_CLK_27M,
  72
  73         GPIO0_B2_SHIFT          = 4,
  74         GPIO0_B2_MASK           = 1,
  75         GPIO0_B2_GPIOB2         = 0,
  76         GPIO0_B2_TSADC_INT,
  77 };
  78
  79 /* PMU_GPIO0_C_IOMUX */
  80 enum {
  81         GPIO0_C1_SHIFT          = 2,
  82         GPIO0_C1_MASK           = 3,
  83         GPIO0_C1_GPIOC1         = 0,
  84         GPIO0_C1_TEST_CLKOUT,
  85         GPIO0_C1_CLKT1_27M,
  86
  87         GPIO0_C0_SHIFT          = 0,
  88         GPIO0_C0_MASK           = 1,
  89         GPIO0_C0_GPIOC0         = 0,
  90         GPIO0_C0_I2C0PMU_SCL,
  91 };
  92
  93 #endif