1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * author: Eric Gao <eric.gao@rock-chips.com>
7 #ifndef ROCKCHIP_MIPI_DSI_H
8 #define ROCKCHIP_MIPI_DSI_H
11 * All these mipi controller register declaration provide reg address offset,
12 * bits width, bit offset for a specified register bits. With these message, we
13 * can set or clear every bits individually for a 32bit widthregister. We use
14 * DSI_HOST_BITS macro definition to combinat these message using the following
15 * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
17 * #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0)
18 * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr
19 * offset is 0x004.The conbinat result = (0x004 << 16) | (1 << 8) | 0
23 #define OFFSET_SHIFT 0
24 #define DSI_HOST_BITS(addr, bits, bit_offset) \
25 ((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT))
27 /* DWC_DSI_VERSION_0x3133302A */
28 #define VERSION DSI_HOST_BITS(0x000, 32, 0)
29 #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0)
30 #define TO_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 8)
31 #define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 0)
32 #define DPI_VCID DSI_HOST_BITS(0x00c, 2, 0)
33 #define EN18_LOOSELY DSI_HOST_BITS(0x010, 1, 8)
34 #define DPI_COLOR_CODING DSI_HOST_BITS(0x010, 4, 0)
35 #define COLORM_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 4)
36 #define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 3)
37 #define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 2)
38 #define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 1)
39 #define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 0)
40 #define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 16)
41 #define INVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 0)
42 #define CRC_RX_EN DSI_HOST_BITS(0x02c, 1, 4)
43 #define ECC_RX_EN DSI_HOST_BITS(0x02c, 1, 3)
44 #define BTA_EN DSI_HOST_BITS(0x02c, 1, 2)
45 #define EOTP_RX_EN DSI_HOST_BITS(0x02c, 1, 1)
46 #define EOTP_TX_EN DSI_HOST_BITS(0x02c, 1, 0)
47 #define GEN_VID_RX DSI_HOST_BITS(0x030, 2, 0)
48 #define CMD_VIDEO_MODE DSI_HOST_BITS(0x034, 1, 0)
49 #define VPG_ORIENTATION DSI_HOST_BITS(0x038, 1, 24)
50 #define VPG_MODE DSI_HOST_BITS(0x038, 1, 20)
51 #define VPG_EN DSI_HOST_BITS(0x038, 1, 16)
52 #define LP_CMD_EN DSI_HOST_BITS(0x038, 1, 15)
53 #define FRAME_BTA_ACK_EN DSI_HOST_BITS(0x038, 1, 14)
54 #define LP_HFP_EN DSI_HOST_BITS(0x038, 1, 13)
55 #define LP_HBP_EN DSI_HOST_BITS(0x038, 1, 12)
56 #define LP_VACT_EN DSI_HOST_BITS(0x038, 1, 11)
57 #define LP_VFP_EN DSI_HOST_BITS(0x038, 1, 10)
58 #define LP_VBP_EN DSI_HOST_BITS(0x038, 1, 9)
59 #define LP_VSA_EN DSI_HOST_BITS(0x038, 1, 8)
60 #define VID_MODE_TYPE DSI_HOST_BITS(0x038, 2, 0)
61 #define VID_PKT_SIZE DSI_HOST_BITS(0x03c, 14, 0)
62 #define NUM_CHUNKS DSI_HOST_BITS(0x040, 13, 0)
63 #define NULL_PKT_SIZE DSI_HOST_BITS(0x044, 13, 0)
64 #define VID_HSA_TIME DSI_HOST_BITS(0x048, 12, 0)
65 #define VID_HBP_TIME DSI_HOST_BITS(0x04c, 12, 0)
66 #define VID_HLINE_TIME DSI_HOST_BITS(0x050, 15, 0)
67 #define VID_VSA_LINES DSI_HOST_BITS(0x054, 10, 0)
68 #define VID_VBP_LINES DSI_HOST_BITS(0x058, 10, 0)
69 #define VID_VFP_LINES DSI_HOST_BITS(0x05c, 10, 0)
70 #define VID_ACTIVE_LINES DSI_HOST_BITS(0x060, 14, 0)
71 #define EDPI_CMD_SIZE DSI_HOST_BITS(0x064, 16, 0)
72 #define MAX_RD_PKT_SIZE DSI_HOST_BITS(0x068, 1, 24)
73 #define DCS_LW_TX DSI_HOST_BITS(0x068, 1, 19)
74 #define DCS_SR_0P_TX DSI_HOST_BITS(0x068, 1, 18)
75 #define DCS_SW_1P_TX DSI_HOST_BITS(0x068, 1, 17)
76 #define DCS_SW_0P_TX DSI_HOST_BITS(0x068, 1, 16)
77 #define GEN_LW_TX DSI_HOST_BITS(0x068, 1, 14)
78 #define GEN_SR_2P_TX DSI_HOST_BITS(0x068, 1, 13)
79 #define GEN_SR_1P_TX DSI_HOST_BITS(0x068, 1, 12)
80 #define GEN_SR_0P_TX DSI_HOST_BITS(0x068, 1, 11)
81 #define GEN_SW_2P_TX DSI_HOST_BITS(0x068, 1, 10)
82 #define GEN_SW_1P_TX DSI_HOST_BITS(0x068, 1, 9)
83 #define GEN_SW_0P_TX DSI_HOST_BITS(0x068, 1, 8)
84 #define ACK_RQST_EN DSI_HOST_BITS(0x068, 1, 1)
85 #define TEAR_FX_EN DSI_HOST_BITS(0x068, 1, 0)
86 #define GEN_WC_MSBYTE DSI_HOST_BITS(0x06c, 14, 16)
87 #define GEN_WC_LSBYTE DSI_HOST_BITS(0x06c, 8, 8)
88 #define GEN_VC DSI_HOST_BITS(0x06c, 2, 6)
89 #define GEN_DT DSI_HOST_BITS(0x06c, 6, 0)
90 #define GEN_PLD_DATA DSI_HOST_BITS(0x070, 32, 0)
91 #define GEN_RD_CMD_BUSY DSI_HOST_BITS(0x074, 1, 6)
92 #define GEN_PLD_R_FULL DSI_HOST_BITS(0x074, 1, 5)
93 #define GEN_PLD_R_EMPTY DSI_HOST_BITS(0x074, 1, 4)
94 #define GEN_PLD_W_FULL DSI_HOST_BITS(0x074, 1, 3)
95 #define GEN_PLD_W_EMPTY DSI_HOST_BITS(0x074, 1, 2)
96 #define GEN_CMD_FULL DSI_HOST_BITS(0x074, 1, 1)
97 #define GEN_CMD_EMPTY DSI_HOST_BITS(0x074, 1, 0)
98 #define HSTX_TO_CNT DSI_HOST_BITS(0x078, 16, 16)
99 #define LPRX_TO_CNT DSI_HOST_BITS(0x078, 16, 0)
100 #define HS_RD_TO_CNT DSI_HOST_BITS(0x07c, 16, 0)
101 #define LP_RD_TO_CNT DSI_HOST_BITS(0x080, 16, 0)
102 #define PRESP_TO_MODE DSI_HOST_BITS(0x084, 1, 24)
103 #define HS_WR_TO_CNT DSI_HOST_BITS(0x084, 16, 0)
104 #define LP_WR_TO_CNT DSI_HOST_BITS(0x088, 16, 0)
105 #define BTA_TO_CNT DSI_HOST_BITS(0x08c, 16, 0)
106 #define AUTO_CLKLANE_CTRL DSI_HOST_BITS(0x094, 1, 1)
107 #define PHY_TXREQUESTCLKHS DSI_HOST_BITS(0x094, 1, 0)
108 #define PHY_HS2LP_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 16)
109 #define PHY_HS2HS_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 0)
110 #define PHY_HS2LP_TIME DSI_HOST_BITS(0x09c, 8, 24)
111 #define PHY_LP2HS_TIME DSI_HOST_BITS(0x09c, 8, 16)
112 #define MAX_RD_TIME DSI_HOST_BITS(0x09c, 15, 0)
113 #define PHY_FORCEPLL DSI_HOST_BITS(0x0a0, 1, 3)
114 #define PHY_ENABLECLK DSI_HOST_BITS(0x0a0, 1, 2)
115 #define PHY_RSTZ DSI_HOST_BITS(0x0a0, 1, 1)
116 #define PHY_SHUTDOWNZ DSI_HOST_BITS(0x0a0, 1, 0)
117 #define PHY_STOP_WAIT_TIME DSI_HOST_BITS(0x0a4, 8, 8)
118 #define N_LANES DSI_HOST_BITS(0x0a4, 2, 0)
119 #define PHY_TXEXITULPSLAN DSI_HOST_BITS(0x0a8, 1, 3)
120 #define PHY_TXREQULPSLAN DSI_HOST_BITS(0x0a8, 1, 2)
121 #define PHY_TXEXITULPSCLK DSI_HOST_BITS(0x0a8, 1, 1)
122 #define PHY_TXREQULPSCLK DSI_HOST_BITS(0x0a8, 1, 0)
123 #define PHY_TX_TRIGGERS DSI_HOST_BITS(0x0ac, 4, 0)
124 #define PHYSTOPSTATECLKLANE DSI_HOST_BITS(0x0b0, 1, 2)
125 #define PHYLOCK DSI_HOST_BITS(0x0b0, 1, 0)
126 #define PHY_TESTCLK DSI_HOST_BITS(0x0b4, 1, 1)
127 #define PHY_TESTCLR DSI_HOST_BITS(0x0b4, 1, 0)
128 #define PHY_TESTEN DSI_HOST_BITS(0x0b8, 1, 16)
129 #define PHY_TESTDOUT DSI_HOST_BITS(0x0b8, 8, 8)
130 #define PHY_TESTDIN DSI_HOST_BITS(0x0b8, 8, 0)
131 #define PHY_TEST_CTRL1 DSI_HOST_BITS(0x0b8, 17, 0)
132 #define PHY_TEST_CTRL0 DSI_HOST_BITS(0x0b4, 2, 0)
133 #define INT_ST0 DSI_HOST_BITS(0x0bc, 21, 0)
134 #define INT_ST1 DSI_HOST_BITS(0x0c0, 18, 0)
135 #define INT_MKS0 DSI_HOST_BITS(0x0c4, 21, 0)
136 #define INT_MKS1 DSI_HOST_BITS(0x0c8, 18, 0)
137 #define INT_FORCE0 DSI_HOST_BITS(0x0d8, 21, 0)
138 #define INT_FORCE1 DSI_HOST_BITS(0x0dc, 18, 0)
140 #define CODE_HS_RX_CLOCK 0x34
141 #define CODE_HS_RX_LANE0 0x44
142 #define CODE_HS_RX_LANE1 0x54
143 #define CODE_HS_RX_LANE2 0x84
144 #define CODE_HS_RX_LANE3 0x94
146 #define CODE_PLL_VCORANGE_VCOCAP 0x10
147 #define CODE_PLL_CPCTRL 0x11
148 #define CODE_PLL_LPF_CP 0x12
149 #define CODE_PLL_INPUT_DIV_RAT 0x17
150 #define CODE_PLL_LOOP_DIV_RAT 0x18
151 #define CODE_PLL_INPUT_LOOP_DIV_RAT 0x19
152 #define CODE_BANDGAP_BIAS_CTRL 0x20
153 #define CODE_TERMINATION_CTRL 0x21
154 #define CODE_AFE_BIAS_BANDGAP_ANOLOG 0x22
156 #define CODE_HSTXDATALANEREQUSETSTATETIME 0x70
157 #define CODE_HSTXDATALANEPREPARESTATETIME 0x71
158 #define CODE_HSTXDATALANEHSZEROSTATETIME 0x72
160 /* Transmission mode between vop and MIPI controller */
161 enum vid_mode_type_t {
162 NON_BURST_SYNC_PLUSE = 0,
163 NON_BURST_SYNC_EVENT,
167 enum cmd_video_mode {
172 /* Indicate MIPI DSI color mode */
173 enum dpi_color_coding {
180 DPI_20BIT_YCBCR_422_LP,
188 /* Indicate which VOP the MIPI DSI use, bit or little one */
194 #endif /* end of ROCKCHIP_MIPI_DSI_H */