2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_SDRAM_RK322X_H
7 #define _ASM_ARCH_SDRAM_RK322X_H
18 struct rk322x_sdram_channel {
20 * bit width in address, eg:
21 * 8 banks using 3 bit to address,
22 * 2 cs using 1 bit to address.
32 #if CONFIG_IS_ENABLED(OF_PLATDATA)
34 * For of-platdata, which would otherwise convert this into two
35 * byte-swapped integers. With a size of 9 bytes, this struct will
36 * appear in of-platdata as a byte array.
38 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
44 struct rk322x_ddr_pctl {
49 u32 reserved0[(0x40 - 0x10) / 4];
55 u32 reserved1[(0x60 - 0x54) / 4];
59 u32 reserved2[(0x7c - 0x6c) / 4];
76 u32 reserved4[(0xc0 - 0xb4) / 4];
113 u32 reserved5[(0x180 - 0x14c) / 4];
118 u32 reserved6[(0x200 - 0x190) / 4];
135 /* dfi control registers */
140 /* dfi write data registers */
143 u32 reserved7[(0x260 - 0x258) / 4];
146 u32 reserved8[(0x270 - 0x268) / 4];
158 u32 reserved10[(0x2ac - 0x29c) / 4];
163 u32 dfitrrdlvlgateen;
173 u32 reserved12[(0x2f0 - 0x2e4) / 4];
176 u32 reserved13[(0x300 - 0x2f4) / 4];
183 u32 dfitrwrlvldelay0;
184 u32 dfitrwrlvldelay1;
185 u32 dfitrwrlvldelay2;
186 u32 dfitrrdlvldelay0;
187 u32 dfitrrdlvldelay1;
188 u32 dfitrrdlvldelay2;
189 u32 dfitrrdlvlgatedelay0;
190 u32 dfitrrdlvlgatedelay1;
191 u32 dfitrrdlvlgatedelay2;
193 u32 reserved14[(0x3f8 - 0x340) / 4];
197 check_member(rk322x_ddr_pctl, iptr, 0x03fc);
199 struct rk322x_ddr_phy {
200 u32 ddrphy_reg[0x100];
203 struct rk322x_pctl_timing {
241 struct rk322x_phy_timing {
248 struct rk322x_msch_timings {
256 struct rk322x_service_sys {
267 struct rk322x_base_params {
268 struct rk322x_msch_timings noc_timing;
280 #define DFI_INIT_START BIT(0)
281 #define DFI_DATA_BYTE_DISABLE_EN BIT(2)
284 #define DFI_DRAM_CLK_SR_EN BIT(0)
285 #define DFI_DRAM_CLK_DPD_EN BIT(1)
288 #define DFI_PARITY_INTR_EN BIT(0)
289 #define DFI_PARITY_EN BIT(1)
292 #define TLP_RESP_TIME_SHIFT 16
293 #define LP_SR_EN BIT(8)
294 #define LP_PD_EN BIT(0)
296 /* PCT_DFITCTRLDELAY */
297 #define TCTRL_DELAY_TIME_SHIFT 0
299 /* PCT_DFITPHYWRDATA */
300 #define TPHY_WRDATA_TIME_SHIFT 0
302 /* PCT_DFITPHYRDLAT */
303 #define TPHY_RDLAT_TIME_SHIFT 0
305 /* PCT_DFITDRAMCLKDIS */
306 #define TDRAM_CLK_DIS_TIME_SHIFT 0
308 /* PCT_DFITDRAMCLKEN */
309 #define TDRAM_CLK_EN_TIME_SHIFT 0
312 #define RANK0_ODT_WRITE_SEL BIT(3)
313 #define RANK1_ODT_WRITE_SEL BIT(11)
315 /* PCTL_DFIODTCFG1 */
316 #define ODT_LEN_BL8_W_SHIFT 16
319 #define ACDLLCR_DLLDIS BIT(31)
320 #define ACDLLCR_DLLSRST BIT(30)
323 #define DXDLLCR_DLLDIS BIT(31)
324 #define DXDLLCR_DLLSRST BIT(30)
327 #define DLLGCR_SBIAS BIT(30)
330 #define DQSRTT BIT(9)
331 #define DQRTT BIT(10)
334 #define PIR_INIT BIT(0)
335 #define PIR_DLLSRST BIT(1)
336 #define PIR_DLLLOCK BIT(2)
337 #define PIR_ZCAL BIT(3)
338 #define PIR_ITMSRST BIT(4)
339 #define PIR_DRAMRST BIT(5)
340 #define PIR_DRAMINIT BIT(6)
341 #define PIR_QSTRN BIT(7)
342 #define PIR_RVTRN BIT(8)
343 #define PIR_ICPC BIT(16)
344 #define PIR_DLLBYP BIT(17)
345 #define PIR_CTLDINIT BIT(18)
346 #define PIR_CLRSR BIT(28)
347 #define PIR_LOCKBYP BIT(29)
348 #define PIR_ZCALBYP BIT(30)
349 #define PIR_INITBYP BIT(31)
352 #define PGCR_DFTLMT_SHIFT 3
353 #define PGCR_DFTCMP_SHIFT 2
354 #define PGCR_DQSCFG_SHIFT 1
355 #define PGCR_ITMDMD_SHIFT 0
358 #define PGSR_IDONE BIT(0)
359 #define PGSR_DLDONE BIT(1)
360 #define PGSR_ZCDONE BIT(2)
361 #define PGSR_DIDONE BIT(3)
362 #define PGSR_DTDONE BIT(4)
363 #define PGSR_DTERR BIT(5)
364 #define PGSR_DTIERR BIT(6)
365 #define PGSR_DFTERR BIT(7)
366 #define PGSR_RVERR BIT(8)
367 #define PGSR_RVEIRR BIT(9)
370 #define PRT_ITMSRST_SHIFT 18
371 #define PRT_DLLLOCK_SHIFT 6
372 #define PRT_DLLSRST_SHIFT 0
375 #define PRT_DINIT0_SHIFT 0
376 #define PRT_DINIT1_SHIFT 19
379 #define PRT_DINIT2_SHIFT 0
380 #define PRT_DINIT3_SHIFT 17
383 #define DDRMD_LPDDR 0
387 #define DDRMD_LPDDR2_LPDDR3 4
389 #define DDRMD_SHIFT 0
394 #define DQSNRES_MASK 0xf
395 #define DQSNRES_SHIFT 8
396 #define DQSRES_MASK 0xf
397 #define DQSRES_SHIFT 4
400 #define TDQSCKMAX_SHIFT 27
401 #define TDQSCKMAX_MASK 7
402 #define TDQSCK_SHIFT 24
403 #define TDQSCK_MASK 7
406 #define DQSGX_SHIFT 5
408 #define DQSGE_SHIFT 8
415 #define SLEEP_STATE 3
416 #define WAKEUP_STATE 4
419 #define LP_TRIG_SHIFT 4
420 #define LP_TRIG_MASK 7
421 #define PCTL_STAT_MASK 7
428 #define LOW_POWER_ENTRY_REQ 6
429 #define LOW_POWER_EXIT_REQ 7
432 #define PD_OUTPUT_SHIFT 0
433 #define PU_OUTPUT_SHIFT 5
434 #define PD_ONDIE_SHIFT 10
435 #define PU_ONDIE_SHIFT 15
436 #define ZDEN_SHIFT 28
439 #define SBIAS_BYPASS BIT(23)
442 #define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
443 #define PD_IDLE_SHIFT 8
444 #define MDDR_EN (2 << 22)
445 #define LPDDR2_EN (3 << 22)
446 #define LPDDR3_EN (1 << 22)
447 #define DDR2_EN (0 << 5)
448 #define DDR3_EN (1 << 5)
449 #define LPDDR2_S2 (0 << 6)
450 #define LPDDR2_S4 (1 << 6)
451 #define MDDR_LPDDR2_BL_2 (0 << 20)
452 #define MDDR_LPDDR2_BL_4 (1 << 20)
453 #define MDDR_LPDDR2_BL_8 (2 << 20)
454 #define MDDR_LPDDR2_BL_16 (3 << 20)
455 #define DDR2_DDR3_BL_4 0
456 #define DDR2_DDR3_BL_8 1
457 #define TFAW_SHIFT 18
458 #define PD_EXIT_SLOW (0 << 17)
459 #define PD_EXIT_FAST (1 << 17)
460 #define PD_TYPE_SHIFT 16
461 #define BURSTLENGTH_SHIFT 20
464 #define POWER_UP_START BIT(0)
467 #define POWER_UP_DONE BIT(0)
482 #define BANK_ADDR_MASK 7
483 #define BANK_ADDR_SHIFT 17
484 #define CMD_ADDR_MASK 0x1fff
485 #define CMD_ADDR_SHIFT 4
487 #define LPDDR23_MA_SHIFT 4
488 #define LPDDR23_MA_MASK 0xff
489 #define LPDDR23_OP_SHIFT 12
490 #define LPDDR23_OP_MASK 0xff
492 #define START_CMD (1u << 31)
498 SOFT_DERESET_ANALOG = 1 << 2,
499 SOFT_DERESET_DIGITAL = 1 << 3,
500 SOFT_RESET_SHIFT = 2,
512 MEMORY_SELECT_DDR3 = 0 << 0,
513 MEMORY_SELECT_LPDDR3 = 2 << 0,
514 MEMORY_SELECT_LPDDR2 = 3 << 0,
515 DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4,
516 DQS_SQU_CAL_SEL_CS1 = 1 << 4,
517 DQS_SQU_CAL_SEL_CS0 = 2 << 4,
518 DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
519 DQS_SQU_CAL_BYPASS_MODE = 1 << 1,
520 DQS_SQU_CAL_START = 1 << 0,
521 DQS_SQU_NO_CAL = 0 << 0,
524 /* CK pull up/down driver strength control */
526 PHY_RON_RTT_DISABLE = 0,
527 PHY_RON_RTT_451OHM = 1,
533 PHY_RON_RTT_64OHM = 7,
535 PHY_RON_RTT_56OHM = 16,
542 PHY_RON_RTT_30OHM = 23,
544 PHY_RON_RTT_28OHM = 24,
551 PHY_RON_RTT_19OHM = 31,
554 /* DQS squelch DLL delay */
556 DQS_DLL_NO_DELAY = 0,
567 #define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0))
568 #define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0))
569 #define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7))
570 #define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7))
572 #define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8))
573 #define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8))
575 #define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6))
576 #define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6))
578 #define PHY_DRV_ODT_SET(n) (((n) << 4) | (n))
579 #define DDR3_DLL_RESET (1 << 8)
581 #endif /* _ASM_ARCH_SDRAM_RK322X_H */