2 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARCH_SDRAM_RK3399_H
8 #define _ASM_ARCH_SDRAM_RK3399_H
18 struct rk3399_ddr_pctl_regs {
22 struct rk3399_ddr_publ_regs {
26 struct rk3399_ddr_pi_regs {
30 struct rk3399_msch_regs {
39 u32 reserved0[(0x110 - 0x20) / 4];
41 u32 reserved1[(0x1000 - 0x114) / 4];
45 struct rk3399_msch_timings {
54 struct rk3399_ddr_cic_regs {
70 #define PWRUP_SREFRESH_EXIT (1 << 16)
73 #define MEM_RST_VALID 1
75 struct rk3399_sdram_channel {
77 /* dram column number, 0 means this channel is invalid */
79 /* dram bank number, 3:8bank, 2:4bank */
81 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
83 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
86 * row_3_4 = 1: 6Gb or 12Gb die
87 * row_3_4 = 0: normal die, power of 2
92 unsigned int ddrconfig;
93 struct rk3399_msch_timings noc_timings;
96 struct rk3399_base_params {
97 unsigned int ddr_freq;
98 unsigned int dramtype;
99 unsigned int num_channels;
104 struct rk3399_sdram_params {
105 struct rk3399_sdram_channel ch[2];
106 struct rk3399_base_params base;
107 struct rk3399_ddr_pctl_regs pctl_regs;
108 struct rk3399_ddr_pi_regs pi_regs;
109 struct rk3399_ddr_publ_regs phy_regs;
112 #define PI_CA_TRAINING (1 << 0)
113 #define PI_WRITE_LEVELING (1 << 1)
114 #define PI_READ_GATE_TRAINING (1 << 2)
115 #define PI_READ_LEVELING (1 << 3)
116 #define PI_WDQ_LEVELING (1 << 4)
117 #define PI_FULL_TRAINING 0xff