1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
6 #ifndef _ASM_ARCH_SDRAM_RK3399_H
7 #define _ASM_ARCH_SDRAM_RK3399_H
17 struct rk3399_ddr_pctl_regs {
21 struct rk3399_ddr_publ_regs {
25 struct rk3399_ddr_pi_regs {
29 struct rk3399_msch_regs {
38 u32 reserved0[(0x110 - 0x20) / 4];
40 u32 reserved1[(0x1000 - 0x114) / 4];
44 struct rk3399_msch_timings {
53 struct rk3399_ddr_cic_regs {
69 #define PWRUP_SREFRESH_EXIT (1 << 16)
72 #define MEM_RST_VALID 1
74 struct rk3399_sdram_channel {
76 /* dram column number, 0 means this channel is invalid */
78 /* dram bank number, 3:8bank, 2:4bank */
80 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
82 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
85 * row_3_4 = 1: 6Gb or 12Gb die
86 * row_3_4 = 0: normal die, power of 2
91 unsigned int ddrconfig;
92 struct rk3399_msch_timings noc_timings;
95 struct rk3399_base_params {
96 unsigned int ddr_freq;
97 unsigned int dramtype;
98 unsigned int num_channels;
103 struct rk3399_sdram_params {
104 struct rk3399_sdram_channel ch[2];
105 struct rk3399_base_params base;
106 struct rk3399_ddr_pctl_regs pctl_regs;
107 struct rk3399_ddr_pi_regs pi_regs;
108 struct rk3399_ddr_publ_regs phy_regs;
111 #define PI_CA_TRAINING (1 << 0)
112 #define PI_WRITE_LEVELING (1 << 1)
113 #define PI_READ_GATE_TRAINING (1 << 2)
114 #define PI_READ_LEVELING (1 << 3)
115 #define PI_WDQ_LEVELING (1 << 4)
116 #define PI_FULL_TRAINING 0xff