1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
6 #ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
7 #define __ARCH_ARM_MACH_S32V234_DDR_H__
12 /* DDR offset in MSCR register */
13 #define _DDR0_RESET 168
14 #define _DDR0_CLK0 169
17 #define _DDR0_WE_B 172
18 #define _DDR0_CKE0 173
19 #define _DDR0_CKE1 174
20 #define _DDR0_CS_B0 175
21 #define _DDR0_CS_B1 176
45 #define _DDR0_DQS0 200
46 #define _DDR0_DQS1 201
47 #define _DDR0_DQS2 202
48 #define _DDR0_DQS3 203
81 #define _DDR0_ODT0 236
82 #define _DDR0_ODT1 237
84 #define _DDR1_RESET 239
85 #define _DDR1_CLK0 240
88 #define _DDR1_WE_B 243
89 #define _DDR1_CKE0 244
90 #define _DDR1_CKE1 245
91 #define _DDR1_CS_B0 246
92 #define _DDR1_CS_B1 247
106 #define _DDR1_A10 261
107 #define _DDR1_A11 262
108 #define _DDR1_A12 263
109 #define _DDR1_A13 264
110 #define _DDR1_A14 265
111 #define _DDR1_A15 266
112 #define _DDR1_DM0 267
113 #define _DDR1_DM1 268
114 #define _DDR1_DM2 269
115 #define _DDR1_DM3 270
116 #define _DDR1_DQS0 271
117 #define _DDR1_DQS1 272
118 #define _DDR1_DQS2 273
119 #define _DDR1_DQS3 274
130 #define _DDR1_D10 285
131 #define _DDR1_D11 286
132 #define _DDR1_D12 287
133 #define _DDR1_D13 288
134 #define _DDR1_D14 289
135 #define _DDR1_D15 290
136 #define _DDR1_D16 291
137 #define _DDR1_D17 292
138 #define _DDR1_D18 293
139 #define _DDR1_D19 294
140 #define _DDR1_D20 295
141 #define _DDR1_D21 296
142 #define _DDR1_D22 297
143 #define _DDR1_D23 298
144 #define _DDR1_D24 299
145 #define _DDR1_D25 300
146 #define _DDR1_D26 301
147 #define _DDR1_D27 302
148 #define _DDR1_D28 303
149 #define _DDR1_D29 304
150 #define _DDR1_D30 305
151 #define _DDR1_D31 306
152 #define _DDR1_ODT0 307
153 #define _DDR1_ODT1 308