2 * (C) Copyright 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __ASM_ARCH_GPIO_H
9 #define __ASM_ARCH_GPIO_H
12 struct s5p_gpio_bank {
18 unsigned int pdn_pull;
19 unsigned char res1[8];
22 /* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
23 enum s5pc100_gpio_pin {
297 S5PC100_GPIO_MAX_PORT
300 enum s5pc110_gpio_pin {
718 S5PC110_GPIO_MAX_PORT
722 unsigned int reg_addr; /* Address of register for this part */
723 unsigned int max_gpio; /* Maximum GPIO in this part */
726 #define S5PC100_GPIO_NUM_PARTS 1
727 static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = {
728 { S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT },
731 #define S5PC110_GPIO_NUM_PARTS 1
732 static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = {
733 { S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT },
736 static inline struct gpio_info *get_gpio_data(void)
738 if (cpu_is_s5pc100())
739 return s5pc100_gpio_data;
740 else if (cpu_is_s5pc110())
741 return s5pc110_gpio_data;
746 static inline unsigned int get_bank_num(void)
748 if (cpu_is_s5pc100())
749 return S5PC100_GPIO_NUM_PARTS;
750 else if (cpu_is_s5pc110())
751 return S5PC110_GPIO_NUM_PARTS;
757 * This structure helps mapping symbolic GPIO names into indices from
758 * exynos5_gpio_pin/exynos5420_gpio_pin enums.
760 * By convention, symbolic GPIO name is defined as follows:
762 * g[p]<bank><set><bit>, where
764 * <bank> - a single character bank name, as defined by the SOC
765 * <set> - a single digit set number
766 * <bit> - bit number within the set (in 0..7 range).
768 * <set><bit> essentially form an octal number of the GPIO pin within the bank
769 * space. On the 5420 architecture some banks' sets do not start not from zero
770 * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
771 * maintain flat number space withoout holes, those banks use offsets to be
772 * deducted from the pin number.
774 struct gpio_name_num_table {
775 char bank; /* bank name symbol */
776 u8 bank_size; /* total number of pins in the bank */
777 char bank_offset; /* offset of the first bank's pin */
778 unsigned int base; /* index of the first bank's pin in the enum */
781 #define GPIO_PER_BANK 8
782 #define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
783 static const struct gpio_name_num_table s5pc100_gpio_table[] = {
784 GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0),
785 GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0),
786 GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0),
787 GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0),
788 GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0),
789 GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0),
790 GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0),
791 GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0),
792 GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0),
793 GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0),
794 GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0),
795 GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0),
799 static const struct gpio_name_num_table s5pc110_gpio_table[] = {
800 GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0),
801 GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0),
802 GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0),
803 GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0),
804 GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0),
805 GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0),
806 GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0),
807 GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0),
808 GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0),
809 GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0),
814 void gpio_cfg_pin(int gpio, int cfg);
815 void gpio_set_pull(int gpio, int mode);
816 void gpio_set_drv(int gpio, int mode);
817 void gpio_set_rate(int gpio, int mode);
818 int s5p_gpio_get_pin(unsigned gpio);
820 /* GPIO pins per bank */
821 #define GPIO_PER_BANK 8
824 /* Pin configurations */
825 #define S5P_GPIO_INPUT 0x0
826 #define S5P_GPIO_OUTPUT 0x1
827 #define S5P_GPIO_IRQ 0xf
828 #define S5P_GPIO_FUNC(x) (x)
831 #define S5P_GPIO_PULL_NONE 0x0
832 #define S5P_GPIO_PULL_DOWN 0x1
833 #define S5P_GPIO_PULL_UP 0x2
835 /* Drive Strength level */
836 #define S5P_GPIO_DRV_1X 0x0
837 #define S5P_GPIO_DRV_3X 0x1
838 #define S5P_GPIO_DRV_2X 0x2
839 #define S5P_GPIO_DRV_4X 0x3
840 #define S5P_GPIO_DRV_FAST 0x0
841 #define S5P_GPIO_DRV_SLOW 0x1