2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CLOCK_MANAGER_H_
8 #define _CLOCK_MANAGER_H_
11 /* Clock speed accessors */
12 unsigned long cm_get_mpu_clk_hz(void);
13 unsigned long cm_get_sdram_clk_hz(void);
14 unsigned int cm_get_l4_sp_clk_hz(void);
15 unsigned int cm_get_mmc_controller_clk_hz(void);
16 unsigned int cm_get_qspi_controller_clk_hz(void);
21 uint32_t main_vco_base;
26 uint32_t mainnandsdmmcclk;
27 uint32_t cfg2fuser0clk;
33 /* peripheral group */
34 uint32_t peri_vco_base;
38 uint32_t pernandsdmmcclk;
46 uint32_t sdram_vco_base;
53 extern void cm_basic_init(const cm_config_t *cfg);
55 struct socfpga_clock_manager_main_pll {
70 u32 _pad_0x38_0x40[2];
73 struct socfpga_clock_manager_per_pll {
87 u32 _pad_0x34_0x40[3];
90 struct socfpga_clock_manager_sdr_pll {
101 struct socfpga_clock_manager_altera {
106 struct socfpga_clock_manager {
113 u32 _pad_0x18_0x3f[10];
114 struct socfpga_clock_manager_main_pll main_pll;
115 struct socfpga_clock_manager_per_pll per_pll;
116 struct socfpga_clock_manager_sdr_pll sdr_pll;
117 struct socfpga_clock_manager_altera altera;
118 u32 _pad_0xe8_0x200[70];
121 #define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
122 #define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
124 #define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
125 #define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
126 #define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
127 #define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
128 #define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
130 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
131 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
132 #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
135 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
136 #define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
137 #define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
138 #define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
139 #define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
140 #define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
141 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
142 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
143 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
144 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
146 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
148 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
150 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
152 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
154 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
156 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
158 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
159 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
160 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
161 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
162 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
163 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
165 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
166 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
167 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
168 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7)
169 #define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
171 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
172 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
174 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
176 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
177 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1)
178 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
179 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
180 #define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
181 #define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
184 #define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
185 #define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
186 #define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
187 #define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
188 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
189 #define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
190 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
191 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
192 #define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
193 #define CLKMGR_VCO_SSRC_EOSC1 0x0
194 #define CLKMGR_VCO_SSRC_EOSC2 0x1
195 #define CLKMGR_VCO_SSRC_F2S 0x2
197 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
199 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
201 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
203 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
205 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
207 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
209 #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
210 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
212 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
213 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
214 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
215 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
216 #define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
218 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
220 #define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
221 #define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4)
222 #define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
223 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
224 #define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0)
225 #define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
226 #define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
227 #define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
228 #define CLKMGR_SDMMC_CLK_SRC_PER 0x2
229 #define CLKMGR_QSPI_CLK_SRC_F2S 0x0
230 #define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
231 #define CLKMGR_QSPI_CLK_SRC_PER 0x2
234 #define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
235 #define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
236 #define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
237 #define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
238 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
239 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
240 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
241 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
242 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
243 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
244 #define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
245 #define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
247 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0)
248 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
249 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
250 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
251 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
253 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
254 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
255 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
256 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
258 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
259 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
260 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
261 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
263 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
264 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
265 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
266 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
268 #define MAIN_VCO_BASE \
269 (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
270 CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
272 #define PERI_VCO_BASE \
273 (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
274 CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
275 CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
277 #define SDR_VCO_BASE \
278 (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
279 CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
280 CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
282 #endif /* _CLOCK_MANAGER_H_ */