1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
11 u32 auto_cfg_reg; /* 0x0 */
12 u32 armdbg_ctr_reg; /* 0x4 */
13 u32 pll1_cntl; /* 0x8 */
14 u32 pll1_frq; /* 0xc */
15 u32 pll1_mod; /* 0x10 */
16 u32 pll2_cntl; /* 0x14 */
17 u32 pll2_frq; /* 0x18 */
18 u32 pll2_mod; /* 0x1C */
19 u32 pll_ctr_reg; /* 0x20 */
20 u32 amba_clk_cfg; /* 0x24 */
21 u32 periph_clk_cfg; /* 0x28 */
22 u32 periph1_clken; /* 0x2C */
23 u32 soc_core_id; /* 0x30 */
24 u32 ras_clken; /* 0x34 */
25 u32 periph1_rst; /* 0x38 */
26 u32 periph2_rst; /* 0x3C */
27 u32 ras_rst; /* 0x40 */
28 u32 prsc1_clk_cfg; /* 0x44 */
29 u32 prsc2_clk_cfg; /* 0x48 */
30 u32 prsc3_clk_cfg; /* 0x4C */
31 u32 amem_cfg_ctrl; /* 0x50 */
32 u32 expi_clk_cfg; /* 0x54 */
33 u32 reserved_1; /* 0x58 */
34 u32 clcd_synth_clk; /* 0x5C */
35 u32 irda_synth_clk; /* 0x60 */
36 u32 uart_synth_clk; /* 0x64 */
37 u32 gmac_synth_clk; /* 0x68 */
38 u32 ras_synth1_clk; /* 0x6C */
39 u32 ras_synth2_clk; /* 0x70 */
40 u32 ras_synth3_clk; /* 0x74 */
41 u32 ras_synth4_clk; /* 0x78 */
42 u32 arb_icm_ml1; /* 0x7C */
43 u32 arb_icm_ml2; /* 0x80 */
44 u32 arb_icm_ml3; /* 0x84 */
45 u32 arb_icm_ml4; /* 0x88 */
46 u32 arb_icm_ml5; /* 0x8C */
47 u32 arb_icm_ml6; /* 0x90 */
48 u32 arb_icm_ml7; /* 0x94 */
49 u32 arb_icm_ml8; /* 0x98 */
50 u32 arb_icm_ml9; /* 0x9C */
51 u32 dma_src_sel; /* 0xA0 */
52 u32 uphy_ctr_reg; /* 0xA4 */
53 u32 gmac_ctr_reg; /* 0xA8 */
54 u32 port_bridge_ctrl; /* 0xAC */
55 u32 reserved_2[4]; /* 0xB0--0xBC */
56 u32 prc1_ilck_ctrl_reg; /* 0xC0 */
57 u32 prc2_ilck_ctrl_reg; /* 0xC4 */
58 u32 prc3_ilck_ctrl_reg; /* 0xC8 */
59 u32 prc4_ilck_ctrl_reg; /* 0xCC */
60 u32 prc1_intr_ctrl_reg; /* 0xD0 */
61 u32 prc2_intr_ctrl_reg; /* 0xD4 */
62 u32 prc3_intr_ctrl_reg; /* 0xD8 */
63 u32 prc4_intr_ctrl_reg; /* 0xDC */
64 u32 powerdown_cfg_reg; /* 0xE0 */
65 u32 ddr_1v8_compensation; /* 0xE4 */
66 u32 ddr_2v5_compensation; /* 0xE8 */
67 u32 core_3v3_compensation; /* 0xEC */
68 u32 ddr_pad; /* 0xF0 */
69 u32 bist1_ctr_reg; /* 0xF4 */
70 u32 bist2_ctr_reg; /* 0xF8 */
71 u32 bist3_ctr_reg; /* 0xFC */
72 u32 bist4_ctr_reg; /* 0x100 */
73 u32 bist5_ctr_reg; /* 0x104 */
74 u32 bist1_rslt_reg; /* 0x108 */
75 u32 bist2_rslt_reg; /* 0x10C */
76 u32 bist3_rslt_reg; /* 0x110 */
77 u32 bist4_rslt_reg; /* 0x114 */
78 u32 bist5_rslt_reg; /* 0x118 */
79 u32 syst_error_reg; /* 0x11C */
80 u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */
81 u32 ras_gpp1_in; /* 0x8000 */
82 u32 ras_gpp2_in; /* 0x8004 */
83 u32 ras_gpp1_out; /* 0x8008 */
84 u32 ras_gpp2_out; /* 0x800C */
88 #define SYNTH23 0x00020003
91 #if defined(CONFIG_SPEAR3XX)
92 #define FREQ_332 0xA600010C
93 #define FREQ_266 0x8500010C
94 #elif defined(CONFIG_SPEAR600)
95 #define FREQ_332 0xA600010F
96 #define FREQ_266 0x8500010F
100 #define MEM_CLK_SEL_MSK 0x70000000
101 #define MEM_CLK_HCLK 0x00000000
102 #define MEM_CLK_2HCLK 0x10000000
103 #define MEM_CLK_PLL2 0x30000000
105 #define EXPI_CLK_CFG_LOW_COMPR 0x2000
106 #define EXPI_CLK_CFG_CLK_EN 0x0400
107 #define EXPI_CLK_CFG_RST 0x0200
108 #define EXPI_CLK_SYNT_EN 0x0010
109 #define EXPI_CLK_CFG_SEL_PLL2 0x0004
110 #define EXPI_CLK_CFG_INT_CLK_EN 0x0001
112 #define PLL2_CNTL_6UA 0x1c00
113 #define PLL2_CNTL_SAMPLE 0x0008
114 #define PLL2_CNTL_ENABLE 0x0004
115 #define PLL2_CNTL_RESETN 0x0002
116 #define PLL2_CNTL_LOCK 0x0001
118 /* AUTO_CFG_REG value */
119 #define MISC_SOCCFGMSK 0x0000003F
120 #define MISC_SOCCFG30 0x0000000C
121 #define MISC_SOCCFG31 0x0000000D
122 #define MISC_NANDDIS 0x00020000
124 /* PERIPH_CLK_CFG value */
125 #define MISC_GPT3SYNTH 0x00000400
126 #define MISC_GPT4SYNTH 0x00000800
127 #define CONFIG_SPEAR_UART48M 0
128 #define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4)
130 /* PRSC_CLK_CFG value */
132 * Fout = Fin / (2^(N+1) * (M + 1))
134 #define MISC_PRSC_N_1 0x00001000
135 #define MISC_PRSC_M_9 0x00000009
136 #define MISC_PRSC_N_4 0x00004000
137 #define MISC_PRSC_M_399 0x0000018F
138 #define MISC_PRSC_N_6 0x00006000
139 #define MISC_PRSC_M_2593 0x00000A21
140 #define MISC_PRSC_M_124 0x0000007C
141 #define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9)
143 /* PERIPH1_CLKEN, PERIPH1_RST value */
144 #define MISC_USBDENB 0x01000000
145 #define MISC_ETHENB 0x00800000
146 #define MISC_SMIENB 0x00200000
147 #define MISC_GPT3ENB 0x00010000
148 #define MISC_GPIO4ENB 0x00002000
149 #define MISC_GPT2ENB 0x00000800
150 #define MISC_FSMCENB 0x00000200
151 #define MISC_I2CENB 0x00000080
152 #define MISC_SSP2ENB 0x00000070
153 #define MISC_UART0ENB 0x00000008
156 #define XTALTIMEEN 0x00000001
157 #define PLLTIMEEN 0x00000002
158 #define CLCDCLK_SYNTH 0x00000000
159 #define CLCDCLK_48MHZ 0x00000004
160 #define CLCDCLK_EXT 0x00000008
161 #define UARTCLK_MASK (0x1 << 4)
162 #define UARTCLK_48MHZ 0x00000000
163 #define UARTCLK_SYNTH 0x00000010
164 #define IRDACLK_48MHZ 0x00000000
165 #define IRDACLK_SYNTH 0x00000020
166 #define IRDACLK_EXT 0x00000040
167 #define RTC_DISABLE 0x00000080
168 #define GPT1CLK_48MHZ 0x00000000
169 #define GPT1CLK_SYNTH 0x00000100
170 #define GPT2CLK_48MHZ 0x00000000
171 #define GPT2CLK_SYNTH 0x00000200
172 #define GPT3CLK_48MHZ 0x00000000
173 #define GPT3CLK_SYNTH 0x00000400
174 #define GPT4CLK_48MHZ 0x00000000
175 #define GPT4CLK_SYNTH 0x00000800
176 #define GPT5CLK_48MHZ 0x00000000
177 #define GPT5CLK_SYNTH 0x00001000
178 #define GPT1_FREEZE 0x00002000
179 #define GPT2_FREEZE 0x00004000
180 #define GPT3_FREEZE 0x00008000
181 #define GPT4_FREEZE 0x00010000
182 #define GPT5_FREEZE 0x00020000
184 /* PERIPH1_CLKEN bits */
185 #define PERIPH_ARM1_WE 0x00000001
186 #define PERIPH_ARM1 0x00000002
187 #define PERIPH_ARM2 0x00000004
188 #define PERIPH_UART1 0x00000008
189 #define PERIPH_UART2 0x00000010
190 #define PERIPH_SSP1 0x00000020
191 #define PERIPH_SSP2 0x00000040
192 #define PERIPH_I2C 0x00000080
193 #define PERIPH_JPEG 0x00000100
194 #define PERIPH_FSMC 0x00000200
195 #define PERIPH_FIRDA 0x00000400
196 #define PERIPH_GPT4 0x00000800
197 #define PERIPH_GPT5 0x00001000
198 #define PERIPH_GPIO4 0x00002000
199 #define PERIPH_SSP3 0x00004000
200 #define PERIPH_ADC 0x00008000
201 #define PERIPH_GPT3 0x00010000
202 #define PERIPH_RTC 0x00020000
203 #define PERIPH_GPIO3 0x00040000
204 #define PERIPH_DMA 0x00080000
205 #define PERIPH_ROM 0x00100000
206 #define PERIPH_SMI 0x00200000
207 #define PERIPH_CLCD 0x00400000
208 #define PERIPH_GMAC 0x00800000
209 #define PERIPH_USBD 0x01000000
210 #define PERIPH_USBH1 0x02000000
211 #define PERIPH_USBH2 0x04000000
212 #define PERIPH_MPMC 0x08000000
213 #define PERIPH_RAMW 0x10000000
214 #define PERIPH_MPMC_EN 0x20000000
215 #define PERIPH_MPMC_WE 0x40000000
216 #define PERIPH_MPMCMSK 0x60000000
218 #define PERIPH_CLK_ALL 0x0FFFFFF8
219 #define PERIPH_RST_ALL 0x00000004
222 #define DDR_PAD_CNF_MSK 0x0000ffff
223 #define DDR_PAD_SW_CONF 0x00060000
224 #define DDR_PAD_SSTL_SEL 0x00000001
225 #define DDR_PAD_DRAM_TYPE 0x00008000
227 /* DDR_COMP values */
228 #define DDR_COMP_ACCURATE 0x00000010
230 /* SoC revision stuff */
231 #define SOC_PRI_SHFT 16
232 #define SOC_SEC_SHFT 8
234 /* Revision definitions */
235 #define SOC_SPEAR_NA 0
238 * The definitons have started from
243 #define SOC_SPEAR600_AA 101
244 #define SOC_SPEAR600_AB 102
245 #define SOC_SPEAR600_BA 103
246 #define SOC_SPEAR600_BB 104
247 #define SOC_SPEAR600_BC 105
248 #define SOC_SPEAR600_BD 106
250 #define SOC_SPEAR300 201
251 #define SOC_SPEAR310 202
252 #define SOC_SPEAR320 203
254 extern int get_socrev(void);
255 int fsmc_nand_switch_ecc(uint32_t eccstrength);