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   1 /*
   2  * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __STI_SDHCI_H__
   8 #define __STI_SDHCI_H__
   9
  10 #define FLASHSS_MMC_CORE_CONFIG_1                       0x400
  11 #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ        BIT(24)
  12 #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN        BIT(12)
  13
  14 #define STI_FLASHSS_MMC_CORE_CONFIG_1                   \
  15         (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ       | \
  16          FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
  17
  18 #define FLASHSS_MMC_CORE_CONFIG_2                       0x404
  19 #define FLASHSS_MMC_CORECFG_HIGH_SPEED                  BIT(28)
  20 #define FLASHSS_MMC_CORECFG_8BIT_EMMC                   BIT(20)
  21 #define MAX_BLK_LENGTH_1024                             BIT(16)
  22 #define BASE_CLK_FREQ_200                               0xc8
  23
  24 #define STI_FLASHSS_MMC_CORE_CONFIG2    \
  25         (FLASHSS_MMC_CORECFG_HIGH_SPEED | \
  26          FLASHSS_MMC_CORECFG_8BIT_EMMC  | \
  27          MAX_BLK_LENGTH_1024            | \
  28          BASE_CLK_FREQ_200 << 0)
  29
  30 #define STI_FLASHSS_SDCARD_CORE_CONFIG2                 \
  31         (FLASHSS_MMC_CORECFG_HIGH_SPEED                 | \
  32          MAX_BLK_LENGTH_1024                            | \
  33          BASE_CLK_FREQ_200)
  34
  35 #define FLASHSS_MMC_CORE_CONFIG_3                       0x408
  36 #define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC              BIT(28)
  37 #define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT         BIT(20)
  38 #define FLASHSS_MMC_CORECFG_3P3_VOLT                    BIT(8)
  39 #define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT            BIT(4)
  40 #define FLASHSS_MMC_CORECFG_SDMA                        BIT(0)
  41
  42 #define STI_FLASHSS_MMC_CORE_CONFIG3                    \
  43          (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC            | \
  44          FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT        | \
  45          FLASHSS_MMC_CORECFG_3P3_VOLT                   | \
  46          FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT           | \
  47          FLASHSS_MMC_CORECFG_SDMA)
  48
  49 #define STI_FLASHSS_SDCARD_CORE_CONFIG3                 \
  50          (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT       | \
  51          FLASHSS_MMC_CORECFG_3P3_VOLT                   | \
  52          FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT           | \
  53          FLASHSS_MMC_CORECFG_SDMA)
  54
  55 #define FLASHSS_MMC_CORE_CONFIG_4                       0x40c
  56 #define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT            BIT(20)
  57 #define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT            BIT(16)
  58 #define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT            BIT(12)
  59
  60 #define STI_FLASHSS_MMC_CORE_CONFIG4                    \
  61         (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT           | \
  62          FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT           | \
  63          FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
  64
  65 #define ST_MMC_CCONFIG_REG_5            0x210
  66 #define SYSCONF_MMC1_ENABLE_BIT         3
  67
  68 #endif  /* _STI_SDHCI_H_ */