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   1 /*
   2  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   3  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __STI_SDHCI_H__
   9 #define __STI_SDHCI_H__
  10
  11 #define FLASHSS_MMC_CORE_CONFIG_1                       0x400
  12 #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ        BIT(24)
  13 #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN        BIT(12)
  14
  15 #define STI_FLASHSS_MMC_CORE_CONFIG_1                   \
  16         (FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ       | \
  17          FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
  18
  19 #define FLASHSS_MMC_CORE_CONFIG_2                       0x404
  20 #define FLASHSS_MMC_CORECFG_HIGH_SPEED                  BIT(28)
  21 #define FLASHSS_MMC_CORECFG_8BIT_EMMC                   BIT(20)
  22 #define MAX_BLK_LENGTH_1024                             BIT(16)
  23 #define BASE_CLK_FREQ_200                               0xc8
  24
  25 #define STI_FLASHSS_MMC_CORE_CONFIG2    \
  26         (FLASHSS_MMC_CORECFG_HIGH_SPEED | \
  27          FLASHSS_MMC_CORECFG_8BIT_EMMC  | \
  28          MAX_BLK_LENGTH_1024            | \
  29          BASE_CLK_FREQ_200 << 0)
  30
  31 #define STI_FLASHSS_SDCARD_CORE_CONFIG2                 \
  32         (FLASHSS_MMC_CORECFG_HIGH_SPEED                 | \
  33          MAX_BLK_LENGTH_1024                            | \
  34          BASE_CLK_FREQ_200)
  35
  36 #define FLASHSS_MMC_CORE_CONFIG_3                       0x408
  37 #define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC              BIT(28)
  38 #define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT         BIT(20)
  39 #define FLASHSS_MMC_CORECFG_3P3_VOLT                    BIT(8)
  40 #define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT            BIT(4)
  41 #define FLASHSS_MMC_CORECFG_SDMA                        BIT(0)
  42
  43 #define STI_FLASHSS_MMC_CORE_CONFIG3                    \
  44          (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC            | \
  45          FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT        | \
  46          FLASHSS_MMC_CORECFG_3P3_VOLT                   | \
  47          FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT           | \
  48          FLASHSS_MMC_CORECFG_SDMA)
  49
  50 #define STI_FLASHSS_SDCARD_CORE_CONFIG3                 \
  51          (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT       | \
  52          FLASHSS_MMC_CORECFG_3P3_VOLT                   | \
  53          FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT           | \
  54          FLASHSS_MMC_CORECFG_SDMA)
  55
  56 #define FLASHSS_MMC_CORE_CONFIG_4                       0x40c
  57 #define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT            BIT(20)
  58 #define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT            BIT(16)
  59 #define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT            BIT(12)
  60
  61 #define STI_FLASHSS_MMC_CORE_CONFIG4                    \
  62         (FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT           | \
  63          FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT           | \
  64          FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
  65
  66 #define ST_MMC_CCONFIG_REG_5            0x210
  67 #define SYSCONF_MMC1_ENABLE_BIT         3
  68
  69 #endif  /* _STI_SDHCI_H_ */