3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
6 * Kamil Lulko, <rev13@wp.pl>
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef _MACH_STM32_H_
12 #define _MACH_STM32_H_
15 * Peripheral memory map
17 #define STM32_SYSMEM_BASE 0x1FFF0000
18 #define STM32_PERIPH_BASE 0x40000000
19 #define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
20 #define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
21 #define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
22 #define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000)
24 #define STM32_BUS_MASK 0xFFFF0000
29 struct stm32_u_id_regs {
35 struct stm32_rcc_regs {
36 u32 cr; /* RCC clock control */
37 u32 pllcfgr; /* RCC PLL configuration */
38 u32 cfgr; /* RCC clock configuration */
39 u32 cir; /* RCC clock interrupt */
40 u32 ahb1rstr; /* RCC AHB1 peripheral reset */
41 u32 ahb2rstr; /* RCC AHB2 peripheral reset */
42 u32 ahb3rstr; /* RCC AHB3 peripheral reset */
44 u32 apb1rstr; /* RCC APB1 peripheral reset */
45 u32 apb2rstr; /* RCC APB2 peripheral reset */
47 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
48 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
49 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
51 u32 apb1enr; /* RCC APB1 peripheral clock enable */
52 u32 apb2enr; /* RCC APB2 peripheral clock enable */
54 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
55 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
56 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
58 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
59 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
61 u32 bdcr; /* RCC Backup domain control */
62 u32 csr; /* RCC clock control & status */
64 u32 sscgr; /* RCC spread spectrum clock generation */
65 u32 plli2scfgr; /* RCC PLLI2S configuration */
70 struct stm32_pwr_regs {
75 struct stm32_flash_regs {
86 * Registers access macros
88 #define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10)
89 #define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE)
91 #define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
92 #define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
94 #define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
95 #define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
97 #define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
98 #define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE)
100 #define STM32_FLASH_SR_BSY (1 << 16)
102 #define STM32_FLASH_CR_PG (1 << 0)
103 #define STM32_FLASH_CR_SER (1 << 1)
104 #define STM32_FLASH_CR_STRT (1 << 16)
105 #define STM32_FLASH_CR_LOCK (1 << 31)
106 #define STM32_FLASH_CR_SNB_OFFSET 3
115 int configure_clocks(void);
116 unsigned long clock_get(enum clock clck);
118 #endif /* _MACH_STM32_H_ */