3 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
6 * Kamil Lulko, <kamil.lulko@gmail.com>
8 * SPDX-License-Identifier: GPL-2.0+
14 struct stm32_fmc_regs {
15 u32 sdcr1; /* Control register 1 */
16 u32 sdcr2; /* Control register 2 */
17 u32 sdtr1; /* Timing register 1 */
18 u32 sdtr2; /* Timing register 2 */
19 u32 sdcmr; /* Mode register */
20 u32 sdrtr; /* Refresh timing register */
21 u32 sdsr; /* Status register */
27 #define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)SDRAM_FMC_BASE)
29 /* Control register SDCR */
30 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
31 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
32 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
33 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
34 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
35 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
36 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
37 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
38 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
40 /* Timings register SDTR */
41 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
42 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
43 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
44 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
45 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
46 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
47 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
50 #define FMC_SDCMR_NRFS_SHIFT 5
52 #define FMC_SDCMR_MODE_NORMAL 0
53 #define FMC_SDCMR_MODE_START_CLOCK 1
54 #define FMC_SDCMR_MODE_PRECHARGE 2
55 #define FMC_SDCMR_MODE_AUTOREFRESH 3
56 #define FMC_SDCMR_MODE_WRITE_MODE 4
57 #define FMC_SDCMR_MODE_SELFREFRESH 5
58 #define FMC_SDCMR_MODE_POWERDOWN 6
60 #define FMC_SDCMR_BANK_1 BIT(4)
61 #define FMC_SDCMR_BANK_2 BIT(3)
63 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9
65 #define FMC_SDSR_BUSY BIT(5)
67 #define FMC_BUSY_WAIT() do { \
68 __asm__ __volatile__ ("dsb" : : : "memory"); \
69 while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
74 #endif /* _MACH_FMC_H_ */