2 * sun6i clock register definitions
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef _SUNXI_CLOCK_SUN6I_H
12 #define _SUNXI_CLOCK_SUN6I_H
14 struct sunxi_ccm_reg {
15 u32 pll1_cfg; /* 0x00 pll1 control */
17 u32 pll2_cfg; /* 0x08 pll2 control */
19 u32 pll3_cfg; /* 0x10 pll3 control */
21 u32 pll4_cfg; /* 0x18 pll4 control */
23 u32 pll5_cfg; /* 0x20 pll5 control */
25 u32 pll6_cfg; /* 0x28 pll6 control */
27 u32 pll7_cfg; /* 0x30 pll7 control */
29 u32 pll8_cfg; /* 0x38 pll8 control */
31 u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
32 u32 pll9_cfg; /* 0x44 pll9 control */
33 u32 pll10_cfg; /* 0x48 pll10 control */
35 u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
36 u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
37 u32 apb2_div; /* 0x58 APB2 divide ratio */
38 u32 axi_gate; /* 0x5c axi module clock gating */
39 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
40 u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
41 u32 apb1_gate; /* 0x68 apb1 module clock gating */
42 u32 apb2_gate; /* 0x6c apb2 module clock gating */
44 u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
45 u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
46 u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
47 u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
48 u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
49 u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
50 u32 ts_clk_cfg; /* 0x98 transport stream clock control */
51 u32 ss_clk_cfg; /* 0x9c security system clock control */
52 u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */
53 u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */
54 u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */
55 u32 spi3_clk_cfg; /* 0xac spi3 clock control */
56 u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/
57 u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
59 u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
61 u32 usb_clk_cfg; /* 0xcc USB clock control */
62 u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
64 u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
65 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
67 u32 dram_clk_gate; /* 0x100 DRAM module gating */
68 u32 be0_clk_cfg; /* 0x104 BE0 module clock */
69 u32 be1_clk_cfg; /* 0x108 BE1 module clock */
70 u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
71 u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
72 u32 mp_clk_cfg; /* 0x114 MP module clock */
73 u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
74 u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
76 u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
77 u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
78 u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */
79 u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */
80 u32 ve_clk_cfg; /* 0x13c VE module clock */
81 u32 adda_clk_cfg; /* 0x140 ADDA module clock */
82 u32 avs_clk_cfg; /* 0x144 AVS module clock */
83 u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
85 u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
86 u32 ps_clk_cfg; /* 0x154 PS module clock */
87 u32 mtc_clk_cfg; /* 0x158 MTC module clock */
88 u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
89 u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
91 u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
92 u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
94 u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */
95 u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */
96 u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */
97 u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */
99 u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */
100 u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */
101 u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */
103 u32 pll_lock; /* 0x200 PLL Lock Time */
104 u32 pll1_lock; /* 0x204 PLL1 Lock Time */
106 u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */
107 u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */
108 u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */
109 u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
110 u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
111 u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
112 u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
113 u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */
114 u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
115 u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
116 u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
118 u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
119 u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
120 u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
121 u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */
122 u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
123 u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
124 u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
125 u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */
126 u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
127 u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
128 u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
130 u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
131 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
132 u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
134 u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
136 u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
140 #define APB2_CLK_SRC_LOSC (0x0 << 24)
141 #define APB2_CLK_SRC_OSC24M (0x1 << 24)
142 #define APB2_CLK_SRC_PLL6 (0x2 << 24)
143 #define APB2_CLK_SRC_MASK (0x3 << 24)
144 #define APB2_CLK_RATE_N_1 (0x0 << 16)
145 #define APB2_CLK_RATE_N_2 (0x1 << 16)
146 #define APB2_CLK_RATE_N_4 (0x2 << 16)
147 #define APB2_CLK_RATE_N_8 (0x3 << 16)
148 #define APB2_CLK_RATE_N_MASK (3 << 16)
149 #define APB2_CLK_RATE_M(m) (((m)-1) << 0)
150 #define APB2_CLK_RATE_M_MASK (0x1f << 0)
152 /* apb2 gate field */
153 #define APB2_GATE_UART_SHIFT (16)
154 #define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT)
155 #define APB2_GATE_TWI_SHIFT (0)
156 #define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
158 /* cpu_axi_cfg bits */
159 #define AXI_DIV_SHIFT 0
160 #define ATB_DIV_SHIFT 8
161 #define CPU_CLK_SRC_SHIFT 16
170 #define CPU_CLK_SRC_OSC24M 1
171 #define CPU_CLK_SRC_PLL1 2
173 #define PLL1_CFG_DEFAULT 0x90011b21
175 #define PLL6_CFG_DEFAULT 0x90041811
177 #define CCM_PLL6_CTRL_N_SHIFT 8
178 #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
179 #define CCM_PLL6_CTRL_K_SHIFT 4
180 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
182 #define AHB_GATE_OFFSET_MMC3 11
183 #define AHB_GATE_OFFSET_MMC2 10
184 #define AHB_GATE_OFFSET_MMC1 9
185 #define AHB_GATE_OFFSET_MMC0 8
186 #define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
188 #define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
189 #define CCM_MMC_CTRL_PLL6 (0x1 << 24)
191 #define CCM_MMC_CTRL_ENABLE (0x1 << 31)
193 #define AHB_RESET_OFFSET_MMC3 11
194 #define AHB_RESET_OFFSET_MMC2 10
195 #define AHB_RESET_OFFSET_MMC1 9
196 #define AHB_RESET_OFFSET_MMC0 8
197 #define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
200 #define APB2_RESET_UART_SHIFT (16)
201 #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
202 #define APB2_RESET_TWI_SHIFT (0)
203 #define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
205 #endif /* _SUNXI_CLOCK_SUN6I_H */