1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * sun8i a83t clock register definitions
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
13 #ifndef _SUNXI_CLOCK_SUN8I_A83T_H
14 #define _SUNXI_CLOCK_SUN8I_A83T_H
16 struct sunxi_ccm_reg {
17 u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */
18 u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */
19 u32 pll2_cfg; /* 0x08 pll2 audio control */
21 u32 pll3_cfg; /* 0x10 pll3 video0 control */
23 u32 pll4_cfg; /* 0x18 pll4 ve control */
25 u32 pll5_cfg; /* 0x20 pll5 ddr control */
27 u32 pll6_cfg; /* 0x28 pll6 peripheral control */
28 u32 reserved5[3]; /* 0x2c */
29 u32 pll7_cfg; /* 0x38 pll7 gpu control */
30 u32 reserved6[2]; /* 0x3c */
31 u32 pll8_cfg; /* 0x44 pll8 hsic control */
32 u32 pll9_cfg; /* 0x48 pll9 de control */
33 u32 pll10_cfg; /* 0x4c pll10 video1 control */
34 u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
35 u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
36 u32 apb2_div; /* 0x58 APB2 divide ratio */
37 u32 ahb2_div; /* 0x5c AHB2 divide ratio */
38 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
39 u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
40 u32 apb1_gate; /* 0x68 apb1 module clock gating 3 */
41 u32 apb2_gate; /* 0x6c apb2 module clock gating 4 */
42 u32 reserved7[2]; /* 0x70 */
43 u32 cci400_cfg; /* 0x78 cci400 clock configuration A83T only */
44 u32 reserved8; /* 0x7c */
45 u32 nand0_clk_cfg; /* 0x80 nand clock control */
46 u32 reserved9; /* 0x84 */
47 u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
48 u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
49 u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
50 u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
51 u32 reserved10; /* 0x98 */
52 u32 ss_clk_cfg; /* 0x9c security system clock control */
53 u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */
54 u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */
55 u32 reserved11[2]; /* 0xa8 */
56 u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control */
57 u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
58 u32 i2s2_clk_cfg; /* 0xb8 I2S2 clock control */
59 u32 tdm_clk_cfg; /* 0xbc TDM clock control */
60 u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
61 u32 reserved12[2]; /* 0xc4 */
62 u32 usb_clk_cfg; /* 0xcc USB clock control */
63 u32 reserved13[9]; /* 0xd0 */
64 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
65 u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register */
66 u32 mbus_reset; /* 0xfc MBUS reset control */
67 u32 dram_clk_gate; /* 0x100 DRAM module gating */
68 u32 reserved14[5]; /* 0x104 BE0 */
69 u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */
70 u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */
71 u32 reserved15[4]; /* 0x120 */
72 u32 mipi_csi_clk_cfg; /* 0x130 MIPI CSI module clock */
73 u32 csi_clk_cfg; /* 0x134 CSI module clock */
74 u32 reserved16; /* 0x138 */
75 u32 ve_clk_cfg; /* 0x13c VE module clock */
76 u32 reserved17; /* 0x140 */
77 u32 avs_clk_cfg; /* 0x144 AVS module clock */
78 u32 reserved18[2]; /* 0x148 */
79 u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
80 u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */
81 u32 reserved19; /* 0x158 */
82 u32 mbus_clk_cfg; /* 0x15c MBUS module clock */
83 u32 reserved20[2]; /* 0x160 */
84 u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
85 u32 reserved21[13]; /* 0x16c */
86 u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */
87 u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */
88 u32 gpu_hyd_clk_cfg; /* 0x1a8 GPU HYD clock config */
89 u32 reserved22[21]; /* 0x1ac */
90 u32 pll_stable0; /* 0x200 PLL stable time 0 */
91 u32 pll_stable1; /* 0x204 PLL stable time 1 */
92 u32 reserved23; /* 0x208 */
93 u32 pll_stable_status; /* 0x20c PLL stable status register */
94 u32 reserved24[4]; /* 0x210 */
95 u32 pll1_c0_bias_cfg; /* 0x220 PLL1 c0cpu# Bias config */
96 u32 pll2_bias_cfg; /* 0x224 PLL2 audio Bias config */
97 u32 pll3_bias_cfg; /* 0x228 PLL3 video Bias config */
98 u32 pll4_bias_cfg; /* 0x22c PLL4 ve Bias config */
99 u32 pll5_bias_cfg; /* 0x230 PLL5 ddr Bias config */
100 u32 pll6_bias_cfg; /* 0x234 PLL6 periph Bias config */
101 u32 pll1_c1_bias_cfg; /* 0x238 PLL1 c1cpu# Bias config */
102 u32 pll8_bias_cfg; /* 0x23c PLL7 Bias config */
103 u32 reserved25; /* 0x240 */
104 u32 pll9_bias_cfg; /* 0x244 PLL9 hsic Bias config */
105 u32 de_bias_cfg; /* 0x248 display engine Bias config */
106 u32 video1_bias_cfg; /* 0x24c pll video1 bias register */
107 u32 c0_tuning_cfg; /* 0x250 pll c0cpu# tuning register */
108 u32 c1_tuning_cfg; /* 0x254 pll c1cpu# tuning register */
109 u32 reserved26[11]; /* 0x258 */
110 u32 pll2_pattern_cfg0; /* 0x284 PLL2 Pattern register 0 */
111 u32 pll3_pattern_cfg0; /* 0x288 PLL3 Pattern register 0 */
112 u32 reserved27; /* 0x28c */
113 u32 pll5_pattern_cfg0; /* 0x290 PLL5 Pattern register 0*/
114 u32 reserved28[4]; /* 0x294 */
115 u32 pll2_pattern_cfg1; /* 0x2a4 PLL2 Pattern register 1 */
116 u32 pll3_pattern_cfg1; /* 0x2a8 PLL3 Pattern register 1 */
117 u32 reserved29; /* 0x2ac */
118 u32 pll5_pattern_cfg1; /* 0x2b0 PLL5 Pattern register 1 */
119 u32 reserved30[3]; /* 0x2b4 */
120 u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
121 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
122 u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
124 u32 ahb_reset3_cfg; /* 0x2d0 AHB1 Reset 3 config */
125 u32 reserved32; /* 0x2d4 */
126 u32 apb2_reset_cfg; /* 0x2d8 BUS Reset 4 config */
130 #define APB2_CLK_SRC_LOSC (0x0 << 24)
131 #define APB2_CLK_SRC_OSC24M (0x1 << 24)
132 #define APB2_CLK_SRC_PLL6 (0x2 << 24)
133 #define APB2_CLK_SRC_MASK (0x3 << 24)
134 #define APB2_CLK_RATE_N_1 (0x0 << 16)
135 #define APB2_CLK_RATE_N_2 (0x1 << 16)
136 #define APB2_CLK_RATE_N_4 (0x2 << 16)
137 #define APB2_CLK_RATE_N_8 (0x3 << 16)
138 #define APB2_CLK_RATE_N_MASK (3 << 16)
139 #define APB2_CLK_RATE_M(m) (((m)-1) << 0)
140 #define APB2_CLK_RATE_M_MASK (0x1f << 0)
142 /* apb2 gate field */
143 #define APB2_GATE_UART_SHIFT (16)
144 #define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT)
145 #define APB2_GATE_TWI_SHIFT (0)
146 #define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
148 /* cpu_axi_cfg bits */
149 #define AXI0_DIV_SHIFT 0
150 #define AXI1_DIV_SHIFT 16
151 #define C0_CPUX_CLK_SRC_SHIFT 12
152 #define C1_CPUX_CLK_SRC_SHIFT 28
158 #define CPU_CLK_SRC_OSC24M 0
159 #define CPU_CLK_SRC_PLL1 1
161 #define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8)
162 #define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16)
163 #define CCM_PLL1_CTRL_EN (0x1 << 31)
164 #define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24)
166 #define PLL8_CFG_DEFAULT 0x42800
167 #define CCM_CCI400_CLK_SEL_HSIC (0x2<<24)
169 #define CCM_PLL5_DIV1_SHIFT 16
170 #define CCM_PLL5_DIV2_SHIFT 18
171 #define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8)
172 #define CCM_PLL5_CTRL_UPD (0x1 << 30)
173 #define CCM_PLL5_CTRL_EN (0x1 << 31)
175 #define PLL6_CFG_DEFAULT 0x80001900 /* 600 MHz */
176 #define CCM_PLL6_CTRL_N_SHIFT 8
177 #define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT)
178 #define CCM_PLL6_CTRL_DIV1_SHIFT 16
179 #define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT)
180 #define CCM_PLL6_CTRL_DIV2_SHIFT 18
181 #define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT)
183 #define AHB1_ABP1_DIV_DEFAULT 0x00002190
184 #define AHB1_CLK_SRC_MASK (0x3<<12)
185 #define AHB1_CLK_SRC_INTOSC (0x0<<12)
186 #define AHB1_CLK_SRC_OSC24M (0x1<<12)
187 #define AHB1_CLK_SRC_PLL6 (0x2<<12)
189 #define AXI_GATE_OFFSET_DRAM 0
191 /* ahb_gate0 offsets */
192 #define AHB_GATE_OFFSET_USB_OHCI1 30
193 #define AHB_GATE_OFFSET_USB_OHCI0 29
194 #define AHB_GATE_OFFSET_USB_EHCI1 27
195 #define AHB_GATE_OFFSET_USB_EHCI0 26
196 #define AHB_GATE_OFFSET_USB0 24
197 #define AHB_GATE_OFFSET_SPI1 21
198 #define AHB_GATE_OFFSET_SPI0 20
199 #define AHB_GATE_OFFSET_HSTIMER 19
200 #define AHB_GATE_OFFSET_EMAC 17
201 #define AHB_GATE_OFFSET_MCTL 14
202 #define AHB_GATE_OFFSET_GMAC 17
203 #define AHB_GATE_OFFSET_NAND0 13
204 #define AHB_GATE_OFFSET_MMC0 8
205 #define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
206 #define AHB_GATE_OFFSET_DMA 6
207 #define AHB_GATE_OFFSET_SS 5
209 /* ahb_gate1 offsets */
210 #define AHB_GATE_OFFSET_DRC0 25
211 #define AHB_GATE_OFFSET_DE_FE0 14
212 #define AHB_GATE_OFFSET_DE_BE0 12
213 #define AHB_GATE_OFFSET_HDMI 11
214 #define AHB_GATE_OFFSET_LCD1 5
215 #define AHB_GATE_OFFSET_LCD0 4
217 #define CCM_MMC_CTRL_M(x) ((x) - 1)
218 #define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
219 #define CCM_MMC_CTRL_N(x) ((x) << 16)
220 #define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
221 #define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
222 #define CCM_MMC_CTRL_PLL6 (0x1 << 24)
223 #define CCM_MMC_CTRL_MODE_SEL_NEW (0x1 << 30)
224 #define CCM_MMC_CTRL_ENABLE (0x1 << 31)
226 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
227 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
228 #define CCM_USB_CTRL_HSIC_RST (0x1 << 2)
229 /* There is no global phy clk gate on sun6i, define as 0 */
230 #define CCM_USB_CTRL_PHYGATE 0
231 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
232 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
233 #define CCM_USB_CTRL_HSIC_CLK (0x1 << 10)
234 #define CCM_USB_CTRL_12M_CLK (0x1 << 11)
235 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
237 #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
238 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
239 #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
240 #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
241 #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
242 #define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
243 #define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
245 #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
247 #define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0)
248 #define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0)
249 #define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
250 #define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
251 #define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
252 #define CCM_DRAMCLK_CFG_RST (0x1 << 31)
254 #define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
255 #define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */
256 #define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16)
258 #define CCM_MBUS_RESET_RESET (0x1 << 31)
260 #define CCM_DRAM_GATE_OFFSET_DE_FE0 24
261 #define CCM_DRAM_GATE_OFFSET_DE_FE1 25
262 #define CCM_DRAM_GATE_OFFSET_DE_BE0 26
263 #define CCM_DRAM_GATE_OFFSET_DE_BE1 27
266 #define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */
268 #define MBUS_CLK_GATE (0x1 << 31)
270 /* ahb_reset0 offsets */
271 #define AHB_RESET_OFFSET_GMAC 17
272 #define AHB_RESET_OFFSET_MCTL 14
273 #define AHB_RESET_OFFSET_MMC3 11
274 #define AHB_RESET_OFFSET_MMC2 10
275 #define AHB_RESET_OFFSET_MMC1 9
276 #define AHB_RESET_OFFSET_MMC0 8
277 #define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
278 #define AHB_RESET_OFFSET_SS 5
280 /* ahb_reset1 offsets */
281 #define AHB_RESET_OFFSET_SAT 26
282 #define AHB_RESET_OFFSET_DRC0 25
283 #define AHB_RESET_OFFSET_DE_FE0 14
284 #define AHB_RESET_OFFSET_DE_BE0 12
285 #define AHB_RESET_OFFSET_HDMI 11
286 #define AHB_RESET_OFFSET_LCD1 5
287 #define AHB_RESET_OFFSET_LCD0 4
289 /* ahb_reset2 offsets */
290 #define AHB_RESET_OFFSET_LVDS 0
293 #define APB2_RESET_UART_SHIFT (16)
294 #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
295 #define APB2_RESET_TWI_SHIFT (0)
296 #define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
300 void clock_set_pll1(unsigned int hz);
301 void clock_set_pll5(unsigned int clk);
302 unsigned int clock_get_pll6(void);
305 #endif /* _SUNXI_CLOCK_SUN8I_A83T_H */