2 * Sunxi platform display controller register and constant defines
4 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _SUNXI_DISPLAY_H
10 #define _SUNXI_DISPLAY_H
12 struct sunxi_de_fe_reg {
13 u32 enable; /* 0x000 */
14 u32 frame_ctrl; /* 0x004 */
15 u32 bypass; /* 0x008 */
16 u32 algorithm_sel; /* 0x00c */
17 u32 line_int_ctrl; /* 0x010 */
18 u8 res0[0x0c]; /* 0x014 */
19 u32 ch0_addr; /* 0x020 */
20 u32 ch1_addr; /* 0x024 */
21 u32 ch2_addr; /* 0x028 */
22 u32 field_sequence; /* 0x02c */
23 u32 ch0_offset; /* 0x030 */
24 u32 ch1_offset; /* 0x034 */
25 u32 ch2_offset; /* 0x038 */
26 u8 res1[0x04]; /* 0x03c */
27 u32 ch0_stride; /* 0x040 */
28 u32 ch1_stride; /* 0x044 */
29 u32 ch2_stride; /* 0x048 */
30 u32 input_fmt; /* 0x04c */
31 u32 ch3_addr; /* 0x050 */
32 u32 ch4_addr; /* 0x054 */
33 u32 ch5_addr; /* 0x058 */
34 u32 output_fmt; /* 0x05c */
35 u32 int_enable; /* 0x060 */
36 u32 int_status; /* 0x064 */
37 u32 status; /* 0x068 */
38 u8 res2[0x04]; /* 0x06c */
39 u32 csc_coef00; /* 0x070 */
40 u32 csc_coef01; /* 0x074 */
41 u32 csc_coef02; /* 0x078 */
42 u32 csc_coef03; /* 0x07c */
43 u32 csc_coef10; /* 0x080 */
44 u32 csc_coef11; /* 0x084 */
45 u32 csc_coef12; /* 0x088 */
46 u32 csc_coef13; /* 0x08c */
47 u32 csc_coef20; /* 0x090 */
48 u32 csc_coef21; /* 0x094 */
49 u32 csc_coef22; /* 0x098 */
50 u32 csc_coef23; /* 0x09c */
51 u32 deinterlace_ctrl; /* 0x0a0 */
52 u32 deinterlace_diag; /* 0x0a4 */
53 u32 deinterlace_tempdiff; /* 0x0a8 */
54 u32 deinterlace_sawtooth; /* 0x0ac */
55 u32 deinterlace_spatcomp; /* 0x0b0 */
56 u32 deinterlace_burstlen; /* 0x0b4 */
57 u32 deinterlace_preluma; /* 0x0b8 */
58 u32 deinterlace_tile_addr; /* 0x0bc */
59 u32 deinterlace_tile_stride; /* 0x0c0 */
60 u8 res3[0x0c]; /* 0x0c4 */
61 u32 wb_stride_enable; /* 0x0d0 */
62 u32 ch3_stride; /* 0x0d4 */
63 u32 ch4_stride; /* 0x0d8 */
64 u32 ch5_stride; /* 0x0dc */
65 u32 fe_3d_ctrl; /* 0x0e0 */
66 u32 fe_3d_ch0_addr; /* 0x0e4 */
67 u32 fe_3d_ch1_addr; /* 0x0e8 */
68 u32 fe_3d_ch2_addr; /* 0x0ec */
69 u32 fe_3d_ch0_offset; /* 0x0f0 */
70 u32 fe_3d_ch1_offset; /* 0x0f4 */
71 u32 fe_3d_ch2_offset; /* 0x0f8 */
72 u8 res4[0x04]; /* 0x0fc */
73 u32 ch0_insize; /* 0x100 */
74 u32 ch0_outsize; /* 0x104 */
75 u32 ch0_horzfact; /* 0x108 */
76 u32 ch0_vertfact; /* 0x10c */
77 u32 ch0_horzphase; /* 0x110 */
78 u32 ch0_vertphase0; /* 0x114 */
79 u32 ch0_vertphase1; /* 0x118 */
80 u8 res5[0x04]; /* 0x11c */
81 u32 ch0_horztapoffset0; /* 0x120 */
82 u32 ch0_horztapoffset1; /* 0x124 */
83 u32 ch0_verttapoffset; /* 0x128 */
84 u8 res6[0xd4]; /* 0x12c */
85 u32 ch1_insize; /* 0x200 */
86 u32 ch1_outsize; /* 0x204 */
87 u32 ch1_horzfact; /* 0x208 */
88 u32 ch1_vertfact; /* 0x20c */
89 u32 ch1_horzphase; /* 0x210 */
90 u32 ch1_vertphase0; /* 0x214 */
91 u32 ch1_vertphase1; /* 0x218 */
92 u8 res7[0x04]; /* 0x21c */
93 u32 ch1_horztapoffset0; /* 0x220 */
94 u32 ch1_horztapoffset1; /* 0x224 */
95 u32 ch1_verttapoffset; /* 0x228 */
96 u8 res8[0x1d4]; /* 0x22c */
97 u32 ch0_horzcoef0[32]; /* 0x400 */
98 u32 ch0_horzcoef1[32]; /* 0x480 */
99 u32 ch0_vertcoef[32]; /* 0x500 */
100 u8 res9[0x80]; /* 0x580 */
101 u32 ch1_horzcoef0[32]; /* 0x600 */
102 u32 ch1_horzcoef1[32]; /* 0x680 */
103 u32 ch1_vertcoef[32]; /* 0x700 */
104 u8 res10[0x280]; /* 0x780 */
105 u32 vpp_enable; /* 0xa00 */
106 u32 vpp_dcti; /* 0xa04 */
107 u32 vpp_lp1; /* 0xa08 */
108 u32 vpp_lp2; /* 0xa0c */
109 u32 vpp_wle; /* 0xa10 */
110 u32 vpp_ble; /* 0xa14 */
113 struct sunxi_de_be_reg {
114 u8 res0[0x800]; /* 0x000 */
115 u32 mode; /* 0x800 */
116 u32 backcolor; /* 0x804 */
117 u32 disp_size; /* 0x808 */
118 u8 res1[0x4]; /* 0x80c */
119 u32 layer0_size; /* 0x810 */
120 u32 layer1_size; /* 0x814 */
121 u32 layer2_size; /* 0x818 */
122 u32 layer3_size; /* 0x81c */
123 u32 layer0_pos; /* 0x820 */
124 u32 layer1_pos; /* 0x824 */
125 u32 layer2_pos; /* 0x828 */
126 u32 layer3_pos; /* 0x82c */
127 u8 res2[0x10]; /* 0x830 */
128 u32 layer0_stride; /* 0x840 */
129 u32 layer1_stride; /* 0x844 */
130 u32 layer2_stride; /* 0x848 */
131 u32 layer3_stride; /* 0x84c */
132 u32 layer0_addr_low32b; /* 0x850 */
133 u32 layer1_addr_low32b; /* 0x854 */
134 u32 layer2_addr_low32b; /* 0x858 */
135 u32 layer3_addr_low32b; /* 0x85c */
136 u32 layer0_addr_high4b; /* 0x860 */
137 u32 layer1_addr_high4b; /* 0x864 */
138 u32 layer2_addr_high4b; /* 0x868 */
139 u32 layer3_addr_high4b; /* 0x86c */
140 u32 reg_ctrl; /* 0x870 */
141 u8 res3[0xc]; /* 0x874 */
142 u32 color_key_max; /* 0x880 */
143 u32 color_key_min; /* 0x884 */
144 u32 color_key_config; /* 0x888 */
145 u8 res4[0x4]; /* 0x88c */
146 u32 layer0_attr0_ctrl; /* 0x890 */
147 u32 layer1_attr0_ctrl; /* 0x894 */
148 u32 layer2_attr0_ctrl; /* 0x898 */
149 u32 layer3_attr0_ctrl; /* 0x89c */
150 u32 layer0_attr1_ctrl; /* 0x8a0 */
151 u32 layer1_attr1_ctrl; /* 0x8a4 */
152 u32 layer2_attr1_ctrl; /* 0x8a8 */
153 u32 layer3_attr1_ctrl; /* 0x8ac */
154 u8 res5[0x110]; /* 0x8b0 */
155 u32 output_color_ctrl; /* 0x9c0 */
156 u8 res6[0xc]; /* 0x9c4 */
157 u32 output_color_coef[12]; /* 0x9d0 */
160 struct sunxi_lcdc_reg {
164 u8 res0[0x04]; /* 0x0c */
165 u32 tcon0_frm_ctrl; /* 0x10 */
166 u32 tcon0_frm_seed[6]; /* 0x14 */
167 u32 tcon0_frm_table[4]; /* 0x2c */
168 u8 res1[4]; /* 0x3c */
169 u32 tcon0_ctrl; /* 0x40 */
170 u32 tcon0_dclk; /* 0x44 */
171 u32 tcon0_timing_active; /* 0x48 */
172 u32 tcon0_timing_h; /* 0x4c */
173 u32 tcon0_timing_v; /* 0x50 */
174 u32 tcon0_timing_sync; /* 0x54 */
175 u32 tcon0_hv_intf; /* 0x58 */
176 u8 res2[0x04]; /* 0x5c */
177 u32 tcon0_cpu_intf; /* 0x60 */
178 u32 tcon0_cpu_wr_dat; /* 0x64 */
179 u32 tcon0_cpu_rd_dat0; /* 0x68 */
180 u32 tcon0_cpu_rd_dat1; /* 0x6c */
181 u32 tcon0_ttl_timing0; /* 0x70 */
182 u32 tcon0_ttl_timing1; /* 0x74 */
183 u32 tcon0_ttl_timing2; /* 0x78 */
184 u32 tcon0_ttl_timing3; /* 0x7c */
185 u32 tcon0_ttl_timing4; /* 0x80 */
186 u32 tcon0_lvds_intf; /* 0x84 */
187 u32 tcon0_io_polarity; /* 0x88 */
188 u32 tcon0_io_tristate; /* 0x8c */
189 u32 tcon1_ctrl; /* 0x90 */
190 u32 tcon1_timing_source; /* 0x94 */
191 u32 tcon1_timing_scale; /* 0x98 */
192 u32 tcon1_timing_out; /* 0x9c */
193 u32 tcon1_timing_h; /* 0xa0 */
194 u32 tcon1_timing_v; /* 0xa4 */
195 u32 tcon1_timing_sync; /* 0xa8 */
196 u8 res3[0x44]; /* 0xac */
197 u32 tcon1_io_polarity; /* 0xf0 */
198 u32 tcon1_io_tristate; /* 0xf4 */
199 u8 res4[0x108]; /* 0xf8 */
200 u32 mux_ctrl; /* 0x200 */
201 u8 res5[0x1c]; /* 0x204 */
202 u32 lvds_ana0; /* 0x220 */
203 u32 lvds_ana1; /* 0x224 */
206 struct sunxi_hdmi_reg {
207 u32 version_id; /* 0x000 */
208 u32 ctrl; /* 0x004 */
211 u32 video_ctrl; /* 0x010 */
212 u32 video_size; /* 0x014 */
213 u32 video_bp; /* 0x018 */
214 u32 video_fp; /* 0x01c */
215 u32 video_spw; /* 0x020 */
216 u32 video_polarity; /* 0x024 */
217 u8 res0[0x58]; /* 0x028 */
218 u8 avi_info_frame[0x14]; /* 0x080 */
219 u8 res1[0x4c]; /* 0x094 */
220 u32 qcp_packet0; /* 0x0e0 */
221 u32 qcp_packet1; /* 0x0e4 */
222 u8 res2[0x118]; /* 0x0e8 */
223 u32 pad_ctrl0; /* 0x200 */
224 u32 pad_ctrl1; /* 0x204 */
225 u32 pll_ctrl; /* 0x208 */
226 u32 pll_dbg0; /* 0x20c */
227 u32 pll_dbg1; /* 0x210 */
228 u32 hpd_cec; /* 0x214 */
229 u8 res3[0x28]; /* 0x218 */
230 u8 vendor_info_frame[0x14]; /* 0x240 */
231 u8 res4[0x9c]; /* 0x254 */
232 u32 pkt_ctrl0; /* 0x2f0 */
233 u32 pkt_ctrl1; /* 0x2f4 */
234 u8 res5[0x8]; /* 0x2f8 */
235 u32 unknown; /* 0x300 */
236 u8 res6[0xc]; /* 0x304 */
237 u32 audio_sample_count; /* 0x310 */
238 u8 res7[0xec]; /* 0x314 */
239 u32 audio_tx_fifo; /* 0x400 */
240 u8 res8[0xfc]; /* 0x404 */
241 #ifndef CONFIG_MACH_SUN6I
242 u32 ddc_ctrl; /* 0x500 */
243 u32 ddc_addr; /* 0x504 */
244 u32 ddc_int_mask; /* 0x508 */
245 u32 ddc_int_status; /* 0x50c */
246 u32 ddc_fifo_ctrl; /* 0x510 */
247 u32 ddc_fifo_status; /* 0x514 */
248 u32 ddc_fifo_data; /* 0x518 */
249 u32 ddc_byte_count; /* 0x51c */
250 u32 ddc_cmnd; /* 0x520 */
251 u32 ddc_exreg; /* 0x524 */
252 u32 ddc_clock; /* 0x528 */
253 u8 res9[0x14]; /* 0x52c */
254 u32 ddc_line_ctrl; /* 0x540 */
256 u32 ddc_ctrl; /* 0x500 */
257 u32 ddc_exreg; /* 0x504 */
258 u32 ddc_cmnd; /* 0x508 */
259 u32 ddc_addr; /* 0x50c */
260 u32 ddc_int_mask; /* 0x510 */
261 u32 ddc_int_status; /* 0x514 */
262 u32 ddc_fifo_ctrl; /* 0x518 */
263 u32 ddc_fifo_status; /* 0x51c */
264 u32 ddc_clock; /* 0x520 */
265 u32 ddc_timeout; /* 0x524 */
266 u8 res9[0x18]; /* 0x528 */
267 u32 ddc_dbg; /* 0x540 */
268 u8 res10[0x3c]; /* 0x544 */
269 u32 ddc_fifo_data; /* 0x580 */
274 * This is based on the A10s User Manual, and the A10s only supports
275 * composite video and not vga like the A10 / A20 does, still other
276 * than the removed vga out capability the tvencoder seems to be the same.
277 * "unknown#" registers are registers which are used in the A10 kernel code,
278 * but not documented in the A10s User Manual.
280 struct sunxi_tve_reg {
281 u32 gctrl; /* 0x000 */
282 u32 cfg0; /* 0x004 */
283 u32 dac_cfg0; /* 0x008 */
284 u32 filter; /* 0x00c */
285 u32 chroma_freq; /* 0x010 */
286 u32 porch_num; /* 0x014 */
287 u32 unknown0; /* 0x018 */
288 u32 line_num; /* 0x01c */
289 u32 blank_black_level; /* 0x020 */
290 u32 unknown1; /* 0x024, seems to be 1 byte per dac */
291 u8 res0[0x08]; /* 0x028 */
292 u32 auto_detect_en; /* 0x030 */
293 u32 auto_detect_int_status; /* 0x034 */
294 u32 auto_detect_status; /* 0x038 */
295 u32 auto_detect_debounce; /* 0x03c */
296 u32 csc_reg0; /* 0x040 */
297 u32 csc_reg1; /* 0x044 */
298 u32 csc_reg2; /* 0x048 */
299 u32 csc_reg3; /* 0x04c */
300 u8 res1[0xb0]; /* 0x050 */
301 u32 color_burst; /* 0x100 */
302 u32 vsync_num; /* 0x104 */
303 u32 notch_freq; /* 0x108 */
304 u32 cbr_level; /* 0x10c */
305 u32 burst_phase; /* 0x110 */
306 u32 burst_width; /* 0x114 */
307 u32 unknown2; /* 0x118 */
308 u32 sync_vbi_level; /* 0x11c */
309 u32 white_level; /* 0x120 */
310 u32 active_num; /* 0x124 */
311 u32 chroma_bw_gain; /* 0x128 */
312 u32 notch_width; /* 0x12c */
313 u32 resync_num; /* 0x130 */
314 u32 slave_para; /* 0x134 */
315 u32 cfg1; /* 0x138 */
316 u32 cfg2; /* 0x13c */
320 * DE-FE register constants.
322 #define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0)
323 #define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16)
324 #define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16)
325 #define SUNXI_DE_FE_ENABLE_EN (1 << 0)
326 #define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0)
327 #define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1)
328 #define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16)
329 #define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1)
330 #define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151
331 #define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002
334 * DE-BE register constants.
336 #define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0)
337 #define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16)
338 #define SUNXI_DE_BE_MODE_ENABLE (1 << 0)
339 #define SUNXI_DE_BE_MODE_START (1 << 1)
340 #define SUNXI_DE_BE_MODE_DEFLICKER_ENABLE (1 << 4)
341 #define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8)
342 #define SUNXI_DE_BE_MODE_INTERLACE_ENABLE (1 << 28)
343 #define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5)
344 #define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0)
345 #define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002
346 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
347 #define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE 1
350 * LCDC register constants.
352 #define SUNXI_LCDC_X(x) (((x) - 1) << 16)
353 #define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
354 #define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24)
355 #define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25)
356 #define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
357 #define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
358 #define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
359 #define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
360 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4))
361 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4))
362 #define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111
363 #define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000
364 #define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111
365 #define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555
366 #define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777
367 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
368 #define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31)
369 #define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0)
370 #define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
371 #define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0)
372 #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16)
373 #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0)
374 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
375 #ifdef CONFIG_SUNXI_GEN_SUN6I
376 #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20)
378 #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */
380 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
381 #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31)
382 #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28)
383 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
384 #define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20)
385 #define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
386 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
387 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
388 #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
389 #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16)
390 #define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0)
391 #define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0)
392 #define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4)
393 #define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4)
394 #ifdef CONFIG_SUNXI_GEN_SUN6I
395 #define SUNXI_LCDC_LVDS_ANA0 0x40040320
396 #define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31)
397 #define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24)
398 #define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20)
400 #define SUNXI_LCDC_LVDS_ANA0 0x3f310000
401 #define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22)
403 #define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10)
404 #define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00)
407 * HDMI register constants.
409 #define SUNXI_HDMI_X(x) (((x) - 1) << 0)
410 #define SUNXI_HDMI_Y(y) (((y) - 1) << 16)
411 #define SUNXI_HDMI_CTRL_ENABLE (1 << 31)
412 #define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0)
413 #define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1)
414 #define SUNXI_HDMI_IRQ_STATUS_BITS 0x73
415 #define SUNXI_HDMI_HPD_DETECT (1 << 0)
416 #define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31)
417 #define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30)
418 #define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0)
419 #define SUNXI_HDMI_VIDEO_POL_VER (1 << 1)
420 #define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16)
421 #define SUNXI_HDMI_QCP_PACKET0 3
422 #define SUNXI_HDMI_QCP_PACKET1 0
424 #ifdef CONFIG_MACH_SUN6I
425 #define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f
426 #define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff
428 #define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000
429 #define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000
432 #ifdef CONFIG_MACH_SUN4I
433 #define SUNXI_HDMI_PAD_CTRL1 0x00d8c820
434 #elif defined CONFIG_MACH_SUN6I
435 #define SUNXI_HDMI_PAD_CTRL1 0x01ded030
437 #define SUNXI_HDMI_PAD_CTRL1 0x00d8c830
439 #define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6)
441 #ifdef CONFIG_MACH_SUN6I
442 #define SUNXI_HDMI_PLL_CTRL 0xba48a308
443 #define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4)
445 #define SUNXI_HDMI_PLL_CTRL 0xfa4ef708
446 #define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4)
448 #define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4)
450 #define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21)
451 #define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21)
453 #define SUNXI_HDMI_PKT_CTRL0 0x00000f21
454 #define SUNXI_HDMI_PKT_CTRL1 0x0000000f
455 #define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000
457 #ifdef CONFIG_MACH_SUN6I
458 #define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0)
459 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4)
460 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6)
461 #define SUNXI_HMDI_DDC_CTRL_START (1 << 27)
462 #define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31)
464 #define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0)
465 /* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
466 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0
467 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0
468 #define SUNXI_HMDI_DDC_CTRL_START (1 << 30)
469 #define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31)
472 #ifdef CONFIG_MACH_SUN6I
473 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0)
475 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0)
477 #define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8)
478 #define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16)
479 #define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24)
481 #ifdef CONFIG_MACH_SUN6I
482 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15)
484 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31)
487 #define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6
488 #define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7
490 #ifdef CONFIG_MACH_SUN6I
491 #define SUNXI_HDMI_DDC_CLOCK 0x61
493 /* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
494 #define SUNXI_HDMI_DDC_CLOCK 0x0d
497 #define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8)
498 #define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9)
501 * TVE register constants.
503 #define SUNXI_TVE_GCTRL_ENABLE (1 << 0)
505 * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
506 * dac from tve1. When using tve1 the mux value must be written to both tve0's
507 * and tve1's gctrl reg.
509 #define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4))
510 #define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4))
511 #define SUNXI_TVE_CFG0_VGA 0x20000000
512 #define SUNXI_TVE_CFG0_PAL 0x07030001
513 #define SUNXI_TVE_CFG0_NTSC 0x07030000
514 #define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7
515 #ifdef CONFIG_MACH_SUN5I
516 #define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009
518 #define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008
520 #define SUNXI_TVE_FILTER_COMPOSITE 0x00000120
521 #define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3
522 #define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446
523 #define SUNXI_TVE_PORCH_NUM_PAL 0x008a0018
524 #define SUNXI_TVE_PORCH_NUM_NTSC 0x00760020
525 #define SUNXI_TVE_LINE_NUM_PAL 0x00160271
526 #define SUNXI_TVE_LINE_NUM_NTSC 0x0016020d
527 #define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL 0x00fc00fc
528 #define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC 0x00f0011a
529 #define SUNXI_TVE_UNKNOWN1_VGA 0x00000000
530 #define SUNXI_TVE_UNKNOWN1_COMPOSITE 0x18181818
531 #define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0))
532 #define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16))
533 #define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0))
534 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8)
535 #define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8))
536 #define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0
537 #define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1
538 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3
539 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8)
540 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8))
541 #define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31)
542 #define SUNXI_TVE_CSC_REG0 0x08440832
543 #define SUNXI_TVE_CSC_REG1 0x3b6dace1
544 #define SUNXI_TVE_CSC_REG2 0x0e1d13dc
545 #define SUNXI_TVE_CSC_REG3 0x00108080
546 #define SUNXI_TVE_COLOR_BURST_PAL_M 0x00000000
547 #define SUNXI_TVE_CBR_LEVEL_PAL 0x00002828
548 #define SUNXI_TVE_CBR_LEVEL_NTSC 0x0000004f
549 #define SUNXI_TVE_BURST_PHASE_NTSC 0x00000000
550 #define SUNXI_TVE_BURST_WIDTH_COMPOSITE 0x0016447e
551 #define SUNXI_TVE_UNKNOWN2_PAL 0x0000e0e0
552 #define SUNXI_TVE_UNKNOWN2_NTSC 0x0000a0a0
553 #define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC 0x001000f0
554 #define SUNXI_TVE_ACTIVE_NUM_COMPOSITE 0x000005a0
555 #define SUNXI_TVE_CHROMA_BW_GAIN_COMP 0x00000002
556 #define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE 0x00000101
557 #define SUNXI_TVE_RESYNC_NUM_PAL 0x800d000c
558 #define SUNXI_TVE_RESYNC_NUM_NTSC 0x000e000c
559 #define SUNXI_TVE_SLAVE_PARA_COMPOSITE 0x00000000
561 int sunxi_simplefb_setup(void *blob);
563 #endif /* _SUNXI_DISPLAY_H */