2 * Sunxi platform display controller register and constant defines
4 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
6 * Based on out of tree Linux DRM driver defines:
7 * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
8 * Copyright (c) 2016 Allwinnertech Co., Ltd.
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef _SUNXI_DISPLAY2_H
14 #define _SUNXI_DISPLAY2_H
16 /* internal clock settings */
111 * DE register constants.
113 #define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000)
114 #define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000)
116 #define SUNXI_DE2_MUX_GLB_REGS 0x00000
117 #define SUNXI_DE2_MUX_BLD_REGS 0x01000
118 #define SUNXI_DE2_MUX_CHAN_REGS 0x02000
119 #define SUNXI_DE2_MUX_CHAN_SZ 0x1000
120 #define SUNXI_DE2_MUX_VSU_REGS 0x20000
121 #define SUNXI_DE2_MUX_GSU1_REGS 0x30000
122 #define SUNXI_DE2_MUX_GSU2_REGS 0x40000
123 #define SUNXI_DE2_MUX_GSU3_REGS 0x50000
124 #define SUNXI_DE2_MUX_FCE_REGS 0xa0000
125 #define SUNXI_DE2_MUX_BWS_REGS 0xa2000
126 #define SUNXI_DE2_MUX_LTI_REGS 0xa4000
127 #define SUNXI_DE2_MUX_PEAK_REGS 0xa6000
128 #define SUNXI_DE2_MUX_ASE_REGS 0xa8000
129 #define SUNXI_DE2_MUX_FCC_REGS 0xaa000
130 #define SUNXI_DE2_MUX_DCSC_REGS 0xb0000
132 #define SUNXI_DE2_FORMAT_XRGB_8888 4
133 #define SUNXI_DE2_FORMAT_RGB_565 10
135 #define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0)
136 #define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0)
137 #define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8)
139 #define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1))
141 #endif /* _SUNXI_DISPLAY2_H */