2 * sun8i H3 platform dram controller register and constant defines
4 * (C) Copyright 2007-2015 Allwinner Technology Co.
5 * Jerry Wang <wangflord@allwinnertech.com>
6 * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
7 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
8 * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef _SUNXI_DRAM_SUN8I_H3_H
14 #define _SUNXI_DRAM_SUN8I_H3_H
16 struct sunxi_mctl_com_reg {
17 u32 cr; /* 0x00 control register */
18 u8 res0[0x8]; /* 0x04 */
19 u32 tmr; /* 0x0c (unused on H3) */
20 u32 mcr[16][2]; /* 0x10 */
21 u32 bwcr; /* 0x90 bandwidth control register */
22 u32 maer; /* 0x94 master enable register */
23 u32 mapr; /* 0x98 master priority register */
25 u32 cpu_bwcr; /* 0xa0 */
26 u32 gpu_bwcr; /* 0xa4 */
27 u32 ve_bwcr; /* 0xa8 */
28 u32 disp_bwcr; /* 0xac */
29 u32 other_bwcr; /* 0xb0 */
30 u32 total_bwcr; /* 0xb4 */
31 u8 res1[0x8]; /* 0xb8 */
33 u32 swoffr; /* 0xc4 */
34 u8 res2[0x8]; /* 0xc8 */
36 u8 res3[0x54]; /* 0xd4 */
37 u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */
38 u8 res4[0x6cc]; /* 0x134 */
39 u32 protect; /* 0x800 */
42 #define MCTL_CR_BL8 (0x4 << 20)
44 #define MCTL_CR_1T (0x1 << 19)
45 #define MCTL_CR_2T (0x0 << 19)
47 #define MCTL_CR_LPDDR3 (0x7 << 16)
48 #define MCTL_CR_LPDDR2 (0x6 << 16)
49 #define MCTL_CR_DDR3 (0x3 << 16)
50 #define MCTL_CR_DDR2 (0x2 << 16)
52 #define MCTL_CR_SEQUENTIAL (0x1 << 15)
53 #define MCTL_CR_INTERLEAVED (0x0 << 15)
55 #define MCTL_CR_32BIT (0x1 << 12)
56 #define MCTL_CR_16BIT (0x0 << 12)
57 #define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT)
59 #define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
60 #define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4)
61 #define MCTL_CR_EIGHT_BANKS (0x1 << 2)
62 #define MCTL_CR_FOUR_BANKS (0x0 << 2)
63 #define MCTL_CR_DUAL_RANK (0x1 << 0)
64 #define MCTL_CR_SINGLE_RANK (0x0 << 0)
66 #define PROTECT_MAGIC (0x94be6fa3)
68 struct sunxi_mctl_ctl_reg {
69 u32 pir; /* 0x00 PHY initialization register */
70 u32 pwrctl; /* 0x04 */
71 u32 mrctrl; /* 0x08 */
73 u32 pgsr[2]; /* 0x10 PHY general status registers */
75 u8 res1[0x14]; /* 0x1c */
76 u32 mr[4]; /* 0x30 mode registers */
77 u32 pllgcr; /* 0x40 */
78 u32 ptr[5]; /* 0x44 PHY timing registers */
79 u32 dramtmg[9]; /* 0x58 DRAM timing registers */
80 u32 odtcfg; /* 0x7c */
81 u32 pitmg[2]; /* 0x80 PHY interface timing registers */
82 u8 res2[0x4]; /* 0x88 */
83 u32 rfshctl0; /* 0x8c */
84 u32 rfshtmg; /* 0x90 refresh timing */
85 u32 rfshctl1; /* 0x94 */
86 u32 pwrtmg; /* 0x98 */
87 u8 res3[0x1c]; /* 0x9c */
88 u32 vtfcr; /* 0xb8 (unused on H3) */
89 u32 dqsgmr; /* 0xbc */
91 u32 dtar[4]; /* 0xc4 */
92 u32 dtdr[2]; /* 0xd4 */
93 u32 dtmr[2]; /* 0xdc */
95 u32 catr[2]; /* 0xe8 */
96 u32 dtedr[2]; /* 0xf0 */
97 u8 res4[0x8]; /* 0xf8 */
98 u32 pgcr[4]; /* 0x100 PHY general configuration registers */
99 u32 iovcr[2]; /* 0x110 */
100 u32 dqsdr; /* 0x118 */
101 u32 dxccr; /* 0x11c */
102 u32 odtmap; /* 0x120 */
103 u32 zqctl[2]; /* 0x124 */
104 u8 res6[0x14]; /* 0x12c */
105 u32 zqcr; /* 0x140 ZQ control register */
106 u32 zqsr; /* 0x144 ZQ status register */
107 u32 zqdr[3]; /* 0x148 ZQ data registers */
108 u8 res7[0x6c]; /* 0x154 */
109 u32 sched; /* 0x1c0 */
110 u32 perfhpr[2]; /* 0x1c4 */
111 u32 perflpr[2]; /* 0x1cc */
112 u32 perfwr[2]; /* 0x1d4 */
113 u8 res8[0x24]; /* 0x1dc */
114 u32 acmdlr; /* 0x200 AC master delay line register */
115 u32 aclcdlr; /* 0x204 AC local calibrated delay line register */
116 u32 aciocr; /* 0x208 AC I/O configuration register */
117 u8 res9[0x4]; /* 0x20c */
118 u32 acbdlr[31]; /* 0x210 AC bit delay line registers */
119 u8 res10[0x74]; /* 0x28c */
120 struct { /* 0x300 DATX8 modules*/
121 u32 mdlr; /* 0x00 master delay line register */
122 u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */
123 u32 bdlr[12]; /* 0x10 bit delay line registers */
124 u32 gtr; /* 0x40 general timing register */
125 u32 gcr; /* 0x44 general configuration register */
126 u32 gsr[3]; /* 0x48 general status registers */
127 u8 res0[0x2c]; /* 0x54 */
129 u8 res11[0x388]; /* 0x500 */
130 u32 upd2; /* 0x888 */
133 #define PTR3_TDINIT1(x) ((x) << 20)
134 #define PTR3_TDINIT0(x) ((x) << 0)
136 #define PTR4_TDINIT3(x) ((x) << 20)
137 #define PTR4_TDINIT2(x) ((x) << 0)
139 #define DRAMTMG0_TWTP(x) ((x) << 24)
140 #define DRAMTMG0_TFAW(x) ((x) << 16)
141 #define DRAMTMG0_TRAS_MAX(x) ((x) << 8)
142 #define DRAMTMG0_TRAS(x) ((x) << 0)
144 #define DRAMTMG1_TXP(x) ((x) << 16)
145 #define DRAMTMG1_TRTP(x) ((x) << 8)
146 #define DRAMTMG1_TRC(x) ((x) << 0)
148 #define DRAMTMG2_TCWL(x) ((x) << 24)
149 #define DRAMTMG2_TCL(x) ((x) << 16)
150 #define DRAMTMG2_TRD2WR(x) ((x) << 8)
151 #define DRAMTMG2_TWR2RD(x) ((x) << 0)
153 #define DRAMTMG3_TMRW(x) ((x) << 16)
154 #define DRAMTMG3_TMRD(x) ((x) << 12)
155 #define DRAMTMG3_TMOD(x) ((x) << 0)
157 #define DRAMTMG4_TRCD(x) ((x) << 24)
158 #define DRAMTMG4_TCCD(x) ((x) << 16)
159 #define DRAMTMG4_TRRD(x) ((x) << 8)
160 #define DRAMTMG4_TRP(x) ((x) << 0)
162 #define DRAMTMG5_TCKSRX(x) ((x) << 24)
163 #define DRAMTMG5_TCKSRE(x) ((x) << 16)
164 #define DRAMTMG5_TCKESR(x) ((x) << 8)
165 #define DRAMTMG5_TCKE(x) ((x) << 0)
167 #define RFSHTMG_TREFI(x) ((x) << 16)
168 #define RFSHTMG_TRFC(x) ((x) << 0)
170 #define PIR_CLRSR (0x1 << 27) /* clear status registers */
171 #define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */
172 #define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */
173 #define PIR_DRAMRST (0x1 << 7) /* DRAM reset */
174 #define PIR_PHYRST (0x1 << 6) /* PHY reset */
175 #define PIR_DCAL (0x1 << 5) /* DDL calibration */
176 #define PIR_PLLINIT (0x1 << 4) /* PLL initialization */
177 #define PIR_ZCAL (0x1 << 1) /* ZQ calibration */
178 #define PIR_INIT (0x1 << 0) /* PHY initialization trigger */
180 #define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */
182 #define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */
184 #define ACBDLR_WRITE_DELAY(x) ((x) << 8)
186 #define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */
187 #define DXBDLR_DM 8 /* DM BDLR index */
188 #define DXBDLR_DQS 9 /* DQS BDLR index */
189 #define DXBDLR_DQSN 10 /* DQSN BDLR index */
191 #define DXBDLR_WRITE_DELAY(x) ((x) << 8)
192 #define DXBDLR_READ_DELAY(x) ((x) << 0)
194 #endif /* _SUNXI_DRAM_SUN8I_H3_H */