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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Sunxi TV encoder register and constant defines
4  *
5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
6  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
7  */
8
9 #ifndef _TVE_H
10 #define _TVE_H
11
12 enum tve_mode {
13         tve_mode_vga,
14         tve_mode_composite_pal,
15         tve_mode_composite_ntsc,
16         tve_mode_composite_pal_m,
17         tve_mode_composite_pal_nc,
18 };
19
20 /*
21  * This is based on the A10s User Manual, and the A10s only supports
22  * composite video and not vga like the A10 / A20 does, still other
23  * than the removed vga out capability the tvencoder seems to be the same.
24  * "unknown#" registers are registers which are used in the A10 kernel code,
25  * but not documented in the A10s User Manual.
26  */
27 struct sunxi_tve_reg {
28         u32 gctrl;                      /* 0x000 */
29         u32 cfg0;                       /* 0x004 */
30         u32 dac_cfg0;                   /* 0x008 */
31         u32 filter;                     /* 0x00c */
32         u32 chroma_freq;                /* 0x010 */
33         u32 porch_num;                  /* 0x014 */
34         u32 unknown0;                   /* 0x018 */
35         u32 line_num;                   /* 0x01c */
36         u32 blank_black_level;          /* 0x020 */
37         u32 unknown1;                   /* 0x024, seems to be 1 byte per dac */
38         u8 res0[0x08];                  /* 0x028 */
39         u32 auto_detect_en;             /* 0x030 */
40         u32 auto_detect_int_status;     /* 0x034 */
41         u32 auto_detect_status;         /* 0x038 */
42         u32 auto_detect_debounce;       /* 0x03c */
43         u32 csc_reg0;                   /* 0x040 */
44         u32 csc_reg1;                   /* 0x044 */
45         u32 csc_reg2;                   /* 0x048 */
46         u32 csc_reg3;                   /* 0x04c */
47         u8 res1[0xb0];                  /* 0x050 */
48         u32 color_burst;                /* 0x100 */
49         u32 vsync_num;                  /* 0x104 */
50         u32 notch_freq;                 /* 0x108 */
51         u32 cbr_level;                  /* 0x10c */
52         u32 burst_phase;                /* 0x110 */
53         u32 burst_width;                /* 0x114 */
54         u32 unknown2;                   /* 0x118 */
55         u32 sync_vbi_level;             /* 0x11c */
56         u32 white_level;                /* 0x120 */
57         u32 active_num;                 /* 0x124 */
58         u32 chroma_bw_gain;             /* 0x128 */
59         u32 notch_width;                /* 0x12c */
60         u32 resync_num;                 /* 0x130 */
61         u32 slave_para;                 /* 0x134 */
62         u32 cfg1;                       /* 0x138 */
63         u32 cfg2;                       /* 0x13c */
64 };
65
66 /*
67  * TVE register constants.
68  */
69 #define SUNXI_TVE_GCTRL_ENABLE                  (1 << 0)
70 /*
71  * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
72  * dac from tve1. When using tve1 the mux value must be written to both tve0's
73  * and tve1's gctrl reg.
74  */
75 #define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac)     (0xf << (((dac) + 1) * 4))
76 #define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel)     ((sel) << (((dac) + 1) * 4))
77 #define SUNXI_TVE_CFG0_VGA                      0x20000000
78 #define SUNXI_TVE_CFG0_PAL                      0x07030001
79 #define SUNXI_TVE_CFG0_NTSC                     0x07030000
80 #define SUNXI_TVE_DAC_CFG0_VGA                  0x403e1ac7
81 #ifdef CONFIG_MACH_SUN5I
82 #define SUNXI_TVE_DAC_CFG0_COMPOSITE            0x433f0009
83 #else
84 #define SUNXI_TVE_DAC_CFG0_COMPOSITE            0x403f0008
85 #endif
86 #define SUNXI_TVE_FILTER_COMPOSITE              0x00000120
87 #define SUNXI_TVE_CHROMA_FREQ_PAL_M             0x21e6efe3
88 #define SUNXI_TVE_CHROMA_FREQ_PAL_NC            0x21f69446
89 #define SUNXI_TVE_PORCH_NUM_PAL                 0x008a0018
90 #define SUNXI_TVE_PORCH_NUM_NTSC                0x00760020
91 #define SUNXI_TVE_LINE_NUM_PAL                  0x00160271
92 #define SUNXI_TVE_LINE_NUM_NTSC                 0x0016020d
93 #define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL         0x00fc00fc
94 #define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC        0x00f0011a
95 #define SUNXI_TVE_UNKNOWN1_VGA                  0x00000000
96 #define SUNXI_TVE_UNKNOWN1_COMPOSITE            0x18181818
97 #define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac)    (1 << ((dac) + 0))
98 #define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac)    (1 << ((dac) + 16))
99 #define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac)   (1 << ((dac) + 0))
100 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8)
101 #define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac)  (3 << ((dac) * 8))
102 #define SUNXI_TVE_AUTO_DETECT_STATUS_NONE       0
103 #define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED  1
104 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND  3
105 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8)
106 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d)  (0xf << ((d) * 8))
107 #define SUNXI_TVE_CSC_REG0_ENABLE               (1 << 31)
108 #define SUNXI_TVE_CSC_REG0                      0x08440832
109 #define SUNXI_TVE_CSC_REG1                      0x3b6dace1
110 #define SUNXI_TVE_CSC_REG2                      0x0e1d13dc
111 #define SUNXI_TVE_CSC_REG3                      0x00108080
112 #define SUNXI_TVE_COLOR_BURST_PAL_M             0x00000000
113 #define SUNXI_TVE_CBR_LEVEL_PAL                 0x00002828
114 #define SUNXI_TVE_CBR_LEVEL_NTSC                0x0000004f
115 #define SUNXI_TVE_BURST_PHASE_NTSC              0x00000000
116 #define SUNXI_TVE_BURST_WIDTH_COMPOSITE         0x0016447e
117 #define SUNXI_TVE_UNKNOWN2_PAL                  0x0000e0e0
118 #define SUNXI_TVE_UNKNOWN2_NTSC                 0x0000a0a0
119 #define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC           0x001000f0
120 #define SUNXI_TVE_ACTIVE_NUM_COMPOSITE          0x000005a0
121 #define SUNXI_TVE_CHROMA_BW_GAIN_COMP           0x00000002
122 #define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE         0x00000101
123 #define SUNXI_TVE_RESYNC_NUM_PAL                0x800d000c
124 #define SUNXI_TVE_RESYNC_NUM_NTSC               0x000e000c
125 #define SUNXI_TVE_SLAVE_PARA_COMPOSITE          0x00000000
126
127 void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode);
128 void tvencoder_enable(struct sunxi_tve_reg * const tve);
129
130 #endif /* _TVE_H */