2 * (C) Copyright 2010-2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 /* Stabilization delays, in usec */
10 #define PLL_STABILIZATION_DELAY (300)
11 #define IO_STABILIZATION_DELAY (1000)
13 #define PLLX_ENABLED (1 << 30)
14 #define CCLK_BURST_POLICY 0x20008888
15 #define SUPER_CCLK_DIVIDER 0x80000000
17 /* Calculate clock fractional divider value from ref and target frequencies */
18 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
20 /* Calculate clock frequency value from reference and clock divider value */
21 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
24 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
25 #define PG_UP_TAG_0 0x0
27 #define CORESIGHT_UNLOCK 0xC5ACCE55;
29 /* AP base physical address of internal SRAM */
30 #define NV_PA_BASE_SRAM 0x40000000
32 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
33 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
34 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
36 #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
37 #define FLOW_MODE_STOP 2
38 #define HALT_COP_EVENT_JTAG (1 << 28)
39 #define HALT_COP_EVENT_IRQ_1 (1 << 11)
40 #define HALT_COP_EVENT_FIQ_1 (1 << 9)
42 /* This is the main entry into U-Boot, used by the Cortex-A9 */
43 extern void _start(void);
46 * Works out the SOC/SKU type used for clocks settings
48 * @return SOC type - see TEGRA_SOC...
50 int tegra_get_chip_sku(void);
53 * Returns the pure SOC (chip ID) from the HIDREV register
55 * @return SOC ID - see CHIPID_TEGRAxx...
57 int tegra_get_chip(void);
60 * Returns the SKU ID from the sku_info register
62 * @return SKU ID - see SKU_ID_Txx...
64 int tegra_get_sku_info(void);
66 /* Do any chip-specific cache config */
67 void config_cache(void);
69 #if defined(CONFIG_TEGRA124)
70 /* Do chip-specific vpr config */
71 void config_vpr(void);
73 static inline void config_vpr(void)