2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Portions Copyright (C) 2011-2012 NVIDIA Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #ifndef __TEGRA_MMC_H_
23 #define __TEGRA_MMC_H_
25 #define TEGRA_SDMMC1_BASE 0xC8000000
26 #define TEGRA_SDMMC2_BASE 0xC8000200
27 #define TEGRA_SDMMC3_BASE 0xC8000400
28 #define TEGRA_SDMMC4_BASE 0xC8000600
30 #define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */
34 unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
35 unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
36 unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
37 unsigned int argument; /* _ARGUMENT_0 */
38 unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
39 unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
40 unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
41 unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
42 unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
43 unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
44 unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
45 unsigned int prnsts; /* _PRESENT_STATE_0 */
46 unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
47 unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
48 unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
49 unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
50 unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
51 unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
52 unsigned char swrst; /* _SW_RESET_ 31:24 */
53 unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
54 unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
55 unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
56 unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
57 unsigned char res1[2]; /* _RESERVED 31:16 */
58 unsigned int capareg; /* _CAPABILITIES_0 */
59 unsigned char res2[4]; /* RESERVED, offset 44h-47h */
60 unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
61 unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
62 unsigned short setacmd12err; /* offset 50h */
63 unsigned short setinterr; /* offset 52h */
64 unsigned char admaerr; /* offset 54h */
65 unsigned char res4[3]; /* RESERVED, offset 55h-57h */
66 unsigned long admaaddr; /* offset 58h-5Fh */
67 unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
68 unsigned short slotintstatus; /* offset FCh */
69 unsigned short hcver; /* HOST Version */
70 unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
73 #define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
74 #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
75 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
76 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
78 #define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
79 #define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
80 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
81 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
82 #define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
84 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
85 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
86 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
87 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
88 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
90 #define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
91 #define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
92 #define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
94 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
95 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
97 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
98 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
99 #define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
101 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
102 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
104 #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
105 #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
106 #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
108 #define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
109 #define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
110 #define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
111 #define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
112 #define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
114 #define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
115 #define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
116 #define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
117 #define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
118 #define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
120 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
123 struct tegra_mmc *reg;
124 int id; /* device id/number, 0-3 */
125 int enabled; /* 1 to enable, 0 to disable */
126 int width; /* Bus Width, 1, 4 or 8 */
127 enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
128 struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */
129 struct fdt_gpio_state pwr_gpio; /* Power GPIO */
130 struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
131 unsigned int version; /* SDHCI spec. version */
132 unsigned int clock; /* Current clock (MHz) */
135 #endif /* __ASSEMBLY__ */
136 #endif /* __TEGRA_MMC_H_ */