2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (c) 2013 NVIDIA Corporation
5 * SPDX-License-Identifier: GPL-2.0+
11 /* USB Controller (USBx_CONTROLLER_) regs */
51 uint periodic_list_base;
58 uint reserved6; /* is this port_sc1 on some controllers? */
65 uint endpt_nak_enable;
76 uint endpt_setup_stat;
82 uint reserved11[0x80];
92 uint periodic_list_base;
117 uint reserved10_1[2];
120 uint reserved10_2[4];
123 uint reserved10_3[4];
126 uint reserved10_4[4];
136 uint endpt_nak_enable;
137 uint endpt_setup_stat;
138 uint reserved11_1[0x7D];
143 uint phy_vbus_sensors;
144 uint phy_vbus_wakeup_id;
145 uint phy_alt_vbus_sys;
147 #ifdef CONFIG_TEGRA20
149 uint usb1_legacy_ctrl;
153 uint ulpi_timing_ctrl_0;
154 uint ulpi_timing_ctrl_1;
159 uint usb1_legacy_ctrl;
167 uint reserved14[64 * 3];
172 uint utmip_xcvr_cfg0;
173 uint utmip_bias_cfg0;
176 uint utmip_hsrx_cfg0;
177 uint utmip_hsrx_cfg1;
178 uint utmip_fslsrx_cfg0;
179 uint utmip_fslsrx_cfg1;
183 uint utmip_misc_cfg0;
184 uint utmip_misc_cfg1;
185 uint utmip_debounce_cfg0;
188 uint utmip_bat_chrg_cfg0;
189 uint utmip_spare_cfg0;
190 uint utmip_xcvr_cfg1;
191 uint utmip_bias_cfg1;
194 /* USB1_LEGACY_CTRL */
195 #define USB1_NO_LEGACY_MODE 1
197 #define VBUS_SENSE_CTL_SHIFT 1
198 #define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
199 #define VBUS_SENSE_CTL_VBUS_WAKEUP 0
200 #define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
201 #define VBUS_SENSE_CTL_AB_SESS_VLD 2
202 #define VBUS_SENSE_CTL_A_SESS_VLD 3
204 /* USBx_IF_USB_SUSP_CTRL_0 */
205 #define UTMIP_PHY_ENB (1 << 12)
206 #define UTMIP_RESET (1 << 11)
207 #define USB_PHY_CLK_VALID (1 << 7)
208 #define USB_SUSP_CLR (1 << 5)
210 #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
211 /* USB2_IF_USB_SUSP_CTRL_0 */
212 #define ULPI_PHY_ENB (1 << 13)
214 /* USB2_IF_ULPI_TIMING_CTRL_0 */
215 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
216 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
218 /* USB2_IF_ULPI_TIMING_CTRL_1 */
219 #define ULPI_DATA_TRIMMER_LOAD (1 << 0)
220 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
221 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
222 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
223 #define ULPI_DIR_TRIMMER_LOAD (1 << 24)
224 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
227 /* USBx_UTMIP_MISC_CFG0 */
228 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
230 /* USBx_UTMIP_MISC_CFG1 */
231 #define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
234 * Tegra 3 and later: Moved to Clock and Reset register space, see
235 * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
237 #define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
238 #define UTMIP_PLLU_STABLE_COUNT_MASK \
239 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
241 * Tegra 3 and later: Moved to Clock and Reset register space, see
242 * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
244 #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
245 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
246 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
248 /* USBx_UTMIP_PLL_CFG1_0 */
249 /* Tegra 3 and later: Moved to Clock and Reset register space */
250 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
251 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
252 (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
253 #define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
254 #define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
256 /* USBx_UTMIP_BIAS_CFG0_0 */
257 #define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
258 #define UTMIP_OTGPD (1 << 11)
259 #define UTMIP_BIASPD (1 << 10)
260 #define UTMIP_HSDISCON_LEVEL_SHIFT 2
261 #define UTMIP_HSDISCON_LEVEL_MASK \
262 (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
263 #define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
264 #define UTMIP_HSSQUELCH_LEVEL_MASK \
265 (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
267 /* USBx_UTMIP_BIAS_CFG1_0 */
268 #define UTMIP_FORCE_PDTRK_POWERDOWN 1
269 #define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8
270 #define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \
271 (0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
272 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
273 #define UTMIP_BIAS_PDTRK_COUNT_MASK \
274 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
276 /* USBx_UTMIP_DEBOUNCE_CFG0_0 */
277 #define UTMIP_DEBOUNCE_CFG0_SHIFT 0
278 #define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
280 /* USBx_UTMIP_TX_CFG0_0 */
281 #define UTMIP_FS_PREAMBLE_J (1 << 19)
283 /* USBx_UTMIP_BAT_CHRG_CFG0_0 */
284 #define UTMIP_PD_CHRG 1
286 /* USBx_UTMIP_SPARE_CFG0_0 */
287 #define FUSE_SETUP_SEL (1 << 3)
289 /* USBx_UTMIP_HSRX_CFG0_0 */
290 #define UTMIP_IDLE_WAIT_SHIFT 15
291 #define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
292 #define UTMIP_ELASTIC_LIMIT_SHIFT 10
293 #define UTMIP_ELASTIC_LIMIT_MASK \
294 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
296 /* USBx_UTMIP_HSRX_CFG1_0 */
297 #define UTMIP_HS_SYNC_START_DLY_SHIFT 1
298 #define UTMIP_HS_SYNC_START_DLY_MASK \
299 (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
301 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
302 #define IC_ENB1 (1 << 3)
304 #ifdef CONFIG_TEGRA20
306 #define PTS1_SHIFT 31
307 #define PTS1_MASK (1 << PTS1_SHIFT)
308 #define STS1 (1 << 30)
310 /* PORTSC, USB2, USB3 */
312 #define PTS_MASK (3U << PTS_SHIFT)
313 #define STS (1 << 29)
315 /* USB2D_HOSTPC1_DEVLC_0 */
317 #define PTS_MASK (0x7U << PTS_SHIFT)
318 #define STS (1 << 28)
322 #define PTS_RESERVED 1
324 #define PTS_ICUSB_SER 3
327 /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
328 #define WKOC (1 << 22)
329 #define WKDS (1 << 21)
330 #define WKCN (1 << 20)
332 /* USBx_UTMIP_XCVR_CFG0_0 */
333 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
334 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
335 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
336 #define UTMIP_XCVR_LSBIAS_SE (1 << 21)
337 #define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
338 #define UTMIP_XCVR_HSSLEW_MSB_MASK \
339 (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
340 #define UTMIP_XCVR_SETUP_MSB_SHIFT 22
341 #define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
342 #define UTMIP_XCVR_SETUP_SHIFT 0
343 #define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
345 /* USBx_UTMIP_XCVR_CFG1_0 */
346 #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
347 #define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
348 (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
349 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
350 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
351 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
353 /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
354 #define VBUS_VLD_STS (1 << 26)
355 #define VBUS_B_SESS_VLD_SW_VALUE (1 << 12)
356 #define VBUS_B_SESS_VLD_SW_EN (1 << 11)
358 /* Setup USB on the board */
359 int usb_process_devicetree(const void *blob);
361 #endif /* _TEGRA_USB_H_ */