2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (c) 2013 NVIDIA Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /* USB1_LEGACY_CTRL */
27 #define USB1_NO_LEGACY_MODE 1
29 #define VBUS_SENSE_CTL_SHIFT 1
30 #define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
31 #define VBUS_SENSE_CTL_VBUS_WAKEUP 0
32 #define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
33 #define VBUS_SENSE_CTL_AB_SESS_VLD 2
34 #define VBUS_SENSE_CTL_A_SESS_VLD 3
36 /* USBx_IF_USB_SUSP_CTRL_0 */
37 #define UTMIP_PHY_ENB (1 << 12)
38 #define UTMIP_RESET (1 << 11)
39 #define USB_PHY_CLK_VALID (1 << 7)
40 #define USB_SUSP_CLR (1 << 5)
42 /* USB2_IF_USB_SUSP_CTRL_0 */
43 #define ULPI_PHY_ENB (1 << 13)
45 /* USBx_UTMIP_MISC_CFG0 */
46 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
48 /* USBx_UTMIP_MISC_CFG1 */
49 #define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
50 #define UTMIP_PLLU_STABLE_COUNT_MASK \
51 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
52 #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
53 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
54 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
55 #define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
57 /* USBx_UTMIP_PLL_CFG1_0 */
58 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
59 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
60 (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
61 #define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
62 #define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
64 /* USBx_UTMIP_BIAS_CFG0_0 */
65 #define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
66 #define UTMIP_OTGPD (1 << 11)
67 #define UTMIP_BIASPD (1 << 10)
68 #define UTMIP_HSDISCON_LEVEL_SHIFT 2
69 #define UTMIP_HSDISCON_LEVEL_MASK \
70 (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
71 #define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
72 #define UTMIP_HSSQUELCH_LEVEL_MASK \
73 (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
75 /* USBx_UTMIP_BIAS_CFG1_0 */
76 #define UTMIP_FORCE_PDTRK_POWERDOWN 1
77 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
78 #define UTMIP_BIAS_PDTRK_COUNT_MASK \
79 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
81 /* USBx_UTMIP_DEBOUNCE_CFG0_0 */
82 #define UTMIP_DEBOUNCE_CFG0_SHIFT 0
83 #define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
85 /* USBx_UTMIP_TX_CFG0_0 */
86 #define UTMIP_FS_PREAMBLE_J (1 << 19)
88 /* USBx_UTMIP_BAT_CHRG_CFG0_0 */
89 #define UTMIP_PD_CHRG 1
91 /* USBx_UTMIP_SPARE_CFG0_0 */
92 #define FUSE_SETUP_SEL (1 << 3)
94 /* USBx_UTMIP_HSRX_CFG0_0 */
95 #define UTMIP_IDLE_WAIT_SHIFT 15
96 #define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
97 #define UTMIP_ELASTIC_LIMIT_SHIFT 10
98 #define UTMIP_ELASTIC_LIMIT_MASK \
99 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
101 /* USBx_UTMIP_HSRX_CFG1_0 */
102 #define UTMIP_HS_SYNC_START_DLY_SHIFT 1
103 #define UTMIP_HS_SYNC_START_DLY_MASK \
104 (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
106 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
107 #define IC_ENB1 (1 << 3)
109 /* PORTSC1, USB1, defined for Tegra20 */
110 #define PTS1_SHIFT 31
111 #define PTS1_MASK (1 << PTS1_SHIFT)
112 #define STS1 (1 << 30)
115 #define PTS_RESERVED 1
117 #define PTS_ICUSB_SER 3
120 /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
121 #define WKOC (1 << 22)
122 #define WKDS (1 << 21)
123 #define WKCN (1 << 20)
125 /* USBx_UTMIP_XCVR_CFG0_0 */
126 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
127 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
128 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
129 #define UTMIP_XCVR_LSBIAS_SE (1 << 21)
130 #define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
131 #define UTMIP_XCVR_HSSLEW_MSB_MASK \
132 (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
133 #define UTMIP_XCVR_SETUP_MSB_SHIFT 22
134 #define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
135 #define UTMIP_XCVR_SETUP_SHIFT 0
136 #define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
138 /* USBx_UTMIP_XCVR_CFG1_0 */
139 #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
140 #define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
141 (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
142 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
143 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
144 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
146 /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
147 #define VBUS_VLD_STS (1 << 26)
150 /* Setup USB on the board */
151 int board_usb_init(const void *blob);
153 #endif /* _TEGRA_USB_H_ */