2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 /* Tegra114 clock PLL tables */
9 #ifndef _TEGRA114_CLOCK_TABLES_H_
10 #define _TEGRA114_CLOCK_TABLES_H_
12 /* The PLLs supported by the hardware */
15 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
22 /* now the simple ones */
23 CLOCK_ID_FIRST_SIMPLE,
24 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
28 /* These are the base clocks (inputs to the Tegra SOC) */
33 CLOCK_ID_COUNT, /* number of PLLs */
34 CLOCK_ID_DISPLAY2, /* placeholder */
38 /* The clocks supported by the hardware */
42 /* Low word: 31:0 (DEVICES_L) */
43 PERIPH_ID_CPU = PERIPH_ID_FIRST,
82 /* Middle word: 63:32 (DEVICES_H) */
113 PERIPH_ID_RESERVED56,
122 /* Upper word 95:64 (DEVICES_U) */
137 PERIPH_ID_RESERVED76,
138 PERIPH_ID_RESERVED77,
139 PERIPH_ID_RESERVED78,
146 PERIPH_ID_RESERVED83,
154 PERIPH_ID_RESERVED89,
156 PERIPH_ID_RESERVED91,
158 PERIPH_ID_RESERVED93,
159 PERIPH_ID_RESERVED94,
160 PERIPH_ID_RESERVED95,
164 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
181 PERIPH_ID_HDA2CODEC2X,
185 PERIPH_ID_EX_RESERVED17,
186 PERIPH_ID_EX_RESERVED18,
187 PERIPH_ID_EX_RESERVED19,
188 PERIPH_ID_EX_RESERVED20,
189 PERIPH_ID_EX_RESERVED21,
190 PERIPH_ID_EX_RESERVED22,
194 PERIPH_ID_EX_RESERVED24,
195 PERIPH_ID_EX_RESERVED25,
196 PERIPH_ID_EX_RESERVED26,
197 PERIPH_ID_EX_RESERVED27,
200 PERIPH_ID_EX_RESERVED30,
201 PERIPH_ID_EX_RESERVED31,
204 PERIPH_ID_HDA2HDMICODEC,
205 PERIPH_ID_RESERVED1_SATACOLD,
206 PERIPH_ID_RESERVED2_PCIERX0,
207 PERIPH_ID_RESERVED3_PCIERX1,
208 PERIPH_ID_RESERVED4_PCIERX2,
209 PERIPH_ID_RESERVED5_PCIERX3,
210 PERIPH_ID_RESERVED6_PCIERX4,
211 PERIPH_ID_RESERVED7_PCIERX5,
215 PERIPH_ID_PCIE2_IOBIST,
216 PERIPH_ID_EMC_IOBIST,
217 PERIPH_ID_HDMI_IOBIST,
218 PERIPH_ID_SATA_IOBIST,
219 PERIPH_ID_MIPI_IOBIST,
220 PERIPH_ID_EMC1_IOBIST,
229 PERIPH_ID_RESERVED21_ENTROPY,
230 PERIPH_ID_RESERVED22_W,
231 PERIPH_ID_RESERVED23_W,
234 PERIPH_ID_RESERVED24_W,
255 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
256 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
257 * confusion bewteen PERIPH_ID_... and PERIPHC_...
259 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
262 enum periphc_internal_id {
335 PERIPHC_G3D2 = PERIPHC_VW_FIRST,
378 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
379 #define PERIPH_REG(id) \
380 (id < PERIPH_ID_VW_FIRST) ? \
381 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
383 /* Mask value for a clock (within PERIPH_REG(id)) */
384 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
386 /* return 1 if a PLL ID is in range */
387 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
389 /* return 1 if a peripheral ID is in range */
390 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
391 (id) < PERIPH_ID_COUNT)
393 #endif /* _TEGRA114_CLOCK_TABLES_H_ */