2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #ifndef _TEGRA114_PINMUX_H_
18 #define _TEGRA114_PINMUX_H_
21 * Pin groups which we adjust. There are three basic attributes of each pin
22 * group which use this enum:
26 * - tristate or normal
29 PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
53 PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
55 PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
58 PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
129 PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
154 PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
189 PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
195 PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
200 PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
202 PINGRP_SDMMC3_CLK_LB_IN,
203 PINGRP_SDMMC3_CLK_LB_OUT,
204 PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
209 PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
216 PDRIVE_PINGROUP_CDEV1,
217 PDRIVE_PINGROUP_CDEV2,
218 PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
219 PDRIVE_PINGROUP_DAP2,
220 PDRIVE_PINGROUP_DAP3,
221 PDRIVE_PINGROUP_DAP4,
223 PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
227 PDRIVE_PINGROUP_UART2,
228 PDRIVE_PINGROUP_UART3,
229 PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
230 PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
232 PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
238 PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
239 PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
240 PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
241 PDRIVE_PINGROUP_DAP5,
242 PDRIVE_PINGROUP_VBUS,
245 PDRIVE_PINGROUP_SDIO4,
247 PDRIVE_PINGROUP_COUNT,
251 * Functions which can be assigned to each of the pin groups. The values here
252 * bear no relation to the values programmed into pinmux registers and are
253 * purely a convenience. The translation is done through a table search.
258 PMUX_FUNC_AUDIO_SYNC,
267 PMUX_FUNC_EMC_TEST0_DLL,
268 PMUX_FUNC_EMC_TEST1_DLL,
313 PMUX_FUNC_VI_SENSOR_CLK,
315 /* End of Tegra2 MUX selectors */
328 PMUX_FUNC_EXTPERIPH1,
329 PMUX_FUNC_EXTPERIPH2,
330 PMUX_FUNC_EXTPERIPH3,
359 /* End of Tegra3 MUX selectors */
367 PMUX_FUNC_RESET_OUT_N,
368 /* End of Tegra114 MUX selectors */
372 PMUX_FUNC_INVALID = 0x4000,
373 PMUX_FUNC_RSVD1 = 0x8000,
374 PMUX_FUNC_RSVD2 = 0x8001,
375 PMUX_FUNC_RSVD3 = 0x8002,
376 PMUX_FUNC_RSVD4 = 0x8003,
379 /* return 1 if a pmux_func is in range */
380 #define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
381 || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
383 /* return 1 if a pingrp is in range */
384 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
386 /* The pullup/pulldown state of a pin group */
388 PMUX_PULL_NORMAL = 0,
392 /* return 1 if a pin_pupd_is in range */
393 #define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
394 ((pupd) <= PMUX_PULL_UP))
396 /* Defines whether a pin group is tristated or in normal operation */
399 PMUX_TRI_TRISTATE = 1,
401 /* return 1 if a pin_tristate_is in range */
402 #define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
403 && ((tristate) <= PMUX_TRI_TRISTATE))
410 /* return 1 if a pin_io_is in range */
411 #define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
412 ((io) <= PMUX_PIN_INPUT))
415 PMUX_PIN_LOCK_DEFAULT = 0,
416 PMUX_PIN_LOCK_DISABLE,
417 PMUX_PIN_LOCK_ENABLE,
419 /* return 1 if a pin_lock is in range */
420 #define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
421 ((lock) <= PMUX_PIN_LOCK_ENABLE))
424 PMUX_PIN_OD_DEFAULT = 0,
428 /* return 1 if a pin_od is in range */
429 #define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
430 ((od) <= PMUX_PIN_OD_ENABLE))
432 enum pmux_pin_ioreset {
433 PMUX_PIN_IO_RESET_DEFAULT = 0,
434 PMUX_PIN_IO_RESET_DISABLE,
435 PMUX_PIN_IO_RESET_ENABLE,
437 /* return 1 if a pin_ioreset_is in range */
438 #define pmux_pin_ioreset_isvalid(ioreset) \
439 (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
440 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
442 enum pmux_pin_rcv_sel {
443 PMUX_PIN_RCV_SEL_DEFAULT = 0,
444 PMUX_PIN_RCV_SEL_NORMAL,
445 PMUX_PIN_RCV_SEL_HIGH,
447 /* return 1 if a pin_rcv_sel_is in range */
448 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
449 (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
450 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
452 #define PGRP_SLWF_NONE -1
453 #define PGRP_SLWF_MAX 3
454 #define PGRP_SLWR_NONE PGRP_SLWF_NONE
455 #define PGRP_SLWR_MAX PGRP_SLWF_MAX
457 #define PGRP_DRVUP_NONE -1
458 #define PGRP_DRVUP_MAX 127
459 #define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
460 #define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
462 #define PGRP_SCHMT_NONE -1
463 #define PGRP_HSM_NONE PGRP_SCHMT_NONE
465 /* return 1 if a padgrp is in range */
466 #define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
468 /* return 1 if a slew-rate rising/falling edge value is in range */
469 #define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
470 (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
472 /* return 1 if a driver output pull-up/down strength code value is in range */
473 #define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
474 (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
476 /* return 1 if a low-power mode value is in range */
477 #define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
478 (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
480 /* Defines a pin group cfg's low-power mode select */
489 /* Defines whether a pin group cfg's schmidt is enabled or not */
491 PGRP_SCHMT_DISABLE = 0,
492 PGRP_SCHMT_ENABLE = 1,
495 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
497 PGRP_HSM_DISABLE = 0,
502 * This defines the configuration for a pin group's pad control config
504 struct padctrl_config {
505 enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
506 int slwf; /* falling edge slew */
507 int slwr; /* rising edge slew */
508 int drvup; /* pull-up drive strength */
509 int drvdn; /* pull-down drive strength */
510 enum pgrp_lpmd lpmd; /* low-power mode selection */
511 enum pgrp_schmt schmt; /* schmidt enable */
512 enum pgrp_hsm hsm; /* high-speed mode enable */
515 /* t114 pin drive group and pin mux registers */
516 #define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
517 #define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
518 PDRIVE_PINGROUP_COUNT)
519 struct pmux_tri_ctlr {
520 uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
521 uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
522 uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
523 uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
524 uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
525 uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
526 uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
528 uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
530 uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
531 uint pmt_reserved5[PMUX_OFFSET];
532 uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
536 * This defines the configuration for a pin, including the function assigned,
537 * pull up/down settings and tristate settings. Having set up one of these
538 * you can call pinmux_config_pingroup() to configure a pin in one step. Also
539 * available is pinmux_config_table() to configure a list of pins.
541 struct pingroup_config {
542 enum pmux_pingrp pingroup; /* pin group PINGRP_... */
543 enum pmux_func func; /* function to assign FUNC_... */
544 enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
545 enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
546 enum pmux_pin_io io; /* input or output PMUX_PIN_... */
547 enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
548 enum pmux_pin_od od; /* open-drain or push-pull driver */
549 enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
550 enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
551 /* VIL/VIH receivers */
554 /* Set a pin group to tristate */
555 void pinmux_tristate_enable(enum pmux_pingrp pin);
557 /* Set a pin group to normal (non tristate) */
558 void pinmux_tristate_disable(enum pmux_pingrp pin);
560 /* Set the pull up/down feature for a pin group */
561 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
563 /* Set the mux function for a pin group */
564 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
566 /* Set the complete configuration for a pin group */
567 void pinmux_config_pingroup(struct pingroup_config *config);
569 /* Set a pin group to tristate or normal */
570 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
572 /* Set a pin group as input or output */
573 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
576 * Configure a list of pin groups
578 * @param config List of config items
579 * @param len Number of config items in list
581 void pinmux_config_table(struct pingroup_config *config, int len);
584 * Set the GP pad configs
586 * @param config List of config items
587 * @param len Number of config items in list
589 void padgrp_config_table(struct padctrl_config *config, int len);
591 #endif /* _TEGRA114_PINMUX_H_ */