3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra124 clock PLL tables */
10 #ifndef _TEGRA124_CLOCK_TABLES_H_
11 #define _TEGRA124_CLOCK_TABLES_H_
13 /* The PLLs supported by the hardware */
16 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
23 /* now the simple ones */
24 CLOCK_ID_FIRST_SIMPLE,
25 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
28 CLOCK_ID_DP, /* Special for Tegra124 */
30 /* These are the base clocks (inputs to the Tegra SoC) */
34 CLOCK_ID_COUNT, /* number of PLLs */
37 * These are clock IDs that are used in table clock_source[][]
38 * but will not be assigned as a clock source for any peripheral.
49 /* The clocks supported by the hardware */
53 /* Low word: 31:0 (DEVICES_L) */
54 PERIPH_ID_CPU = PERIPH_ID_FIRST,
93 /* Middle word: 63:32 (DEVICES_H) */
100 PERIPH_ID_RESERVED38,
107 PERIPH_ID_RESERVED43,
115 PERIPH_ID_RESERVED49,
119 PERIPH_ID_RESERVED53,
128 PERIPH_ID_RESERVED60,
133 /* Upper word 95:64 (DEVICES_U) */
134 PERIPH_ID_RESERVED64,
149 PERIPH_ID_TRACECLKIN,
154 PERIPH_ID_RESERVED80,
158 PERIPH_ID_RESERVED84,
159 PERIPH_ID_RESERVED85,
160 PERIPH_ID_RESERVED86,
164 PERIPH_ID_RESERVED88,
166 PERIPH_ID_RESERVED90,
168 PERIPH_ID_RESERVED92,
169 PERIPH_ID_RESERVED93,
170 PERIPH_ID_RESERVED94,
175 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
177 PERIPH_ID_V_RESERVED2,
179 PERIPH_ID_V_RESERVED4,
192 PERIPH_ID_HDA2CODEC2X,
196 PERIPH_ID_V_RESERVED17,
197 PERIPH_ID_V_RESERVED18,
198 PERIPH_ID_V_RESERVED19,
199 PERIPH_ID_V_RESERVED20,
200 PERIPH_ID_V_RESERVED21,
201 PERIPH_ID_V_RESERVED22,
205 PERIPH_ID_EXTPERIPH1,
206 PERIPH_ID_EXTPERIPH2,
207 PERIPH_ID_EXTPERIPH3,
211 PERIPH_ID_V_RESERVED30,
212 PERIPH_ID_V_RESERVED31,
215 PERIPH_ID_HDA2HDMICODEC,
217 PERIPH_ID_W_RESERVED2,
218 PERIPH_ID_W_RESERVED3,
219 PERIPH_ID_W_RESERVED4,
220 PERIPH_ID_W_RESERVED5,
221 PERIPH_ID_W_RESERVED6,
222 PERIPH_ID_W_RESERVED7,
226 PERIPH_ID_W_RESERVED9,
227 PERIPH_ID_W_RESERVED10,
228 PERIPH_ID_W_RESERVED11,
229 PERIPH_ID_W_RESERVED12,
230 PERIPH_ID_W_RESERVED13,
231 PERIPH_ID_XUSB_PADCTL,
232 PERIPH_ID_W_RESERVED15,
235 PERIPH_ID_W_RESERVED16,
236 PERIPH_ID_W_RESERVED17,
237 PERIPH_ID_W_RESERVED18,
238 PERIPH_ID_W_RESERVED19,
239 PERIPH_ID_W_RESERVED20,
242 PERIPH_ID_W_RESERVED23,
250 PERIPH_ID_W_RESERVED29,
251 PERIPH_ID_W_RESERVED30,
252 PERIPH_ID_W_RESERVED31,
256 PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
257 PERIPH_ID_X_RESERVED1,
258 PERIPH_ID_X_RESERVED2,
259 PERIPH_ID_X_RESERVED3,
263 PERIPH_ID_X_RESERVED7,
266 PERIPH_ID_X_RESERVED8,
267 PERIPH_ID_X_RESERVED9,
268 PERIPH_ID_X_RESERVED10,
270 PERIPH_ID_X_RESERVED12,
271 PERIPH_ID_X_RESERVED13,
273 PERIPH_ID_X_RESERVED15,
276 PERIPH_ID_HDMI_AUDIO,
279 PERIPH_ID_X_RESERVED19,
283 PERIPH_ID_X_RESERVED23,
288 PERIPH_ID_X_RESERVED26,
289 PERIPH_ID_X_RESERVED27,
290 PERIPH_ID_X_RESERVED28,
291 PERIPH_ID_X_RESERVED29,
292 PERIPH_ID_X_RESERVED30,
293 PERIPH_ID_X_RESERVED31,
307 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
308 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
309 * confusion bewteen PERIPH_ID_... and PERIPHC_...
311 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
314 enum periphc_internal_id {
397 PERIPHC_40h = PERIPHC_VW_FIRST,
433 PERIPHC_HDA, /* 0x428 */
438 PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
441 PERIPHC_XUSB_CORE_DEV,
482 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
483 #define PERIPH_REG(id) \
484 (id < PERIPH_ID_VW_FIRST) ? \
485 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
487 /* Mask value for a clock (within PERIPH_REG(id)) */
488 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
490 /* return 1 if a PLL ID is in range */
491 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
493 /* return 1 if a peripheral ID is in range */
494 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
495 (id) < PERIPH_ID_COUNT)
497 #endif /* _TEGRA124_CLOCK_TABLES_H_ */