3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra124 clock PLL tables */
10 #ifndef _TEGRA124_CLOCK_TABLES_H_
11 #define _TEGRA124_CLOCK_TABLES_H_
13 /* The PLLs supported by the hardware */
16 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
23 /* now the simple ones */
24 CLOCK_ID_FIRST_SIMPLE,
25 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
28 CLOCK_ID_DP, /* Special for Tegra124 */
30 /* These are the base clocks (inputs to the Tegra SoC) */
35 CLOCK_ID_COUNT, /* number of PLLs */
38 * These are clock IDs that are used in table clock_source[][]
39 * but will not be assigned as a clock source for any peripheral.
50 /* The clocks supported by the hardware */
54 /* Low word: 31:0 (DEVICES_L) */
55 PERIPH_ID_CPU = PERIPH_ID_FIRST,
94 /* Middle word: 63:32 (DEVICES_H) */
101 PERIPH_ID_RESERVED38,
108 PERIPH_ID_RESERVED43,
116 PERIPH_ID_RESERVED49,
120 PERIPH_ID_RESERVED53,
129 PERIPH_ID_RESERVED60,
134 /* Upper word 95:64 (DEVICES_U) */
135 PERIPH_ID_RESERVED64,
150 PERIPH_ID_TRACECLKIN,
155 PERIPH_ID_RESERVED80,
159 PERIPH_ID_RESERVED84,
160 PERIPH_ID_RESERVED85,
161 PERIPH_ID_RESERVED86,
165 PERIPH_ID_RESERVED88,
167 PERIPH_ID_RESERVED90,
169 PERIPH_ID_RESERVED92,
170 PERIPH_ID_RESERVED93,
171 PERIPH_ID_RESERVED94,
176 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
178 PERIPH_ID_V_RESERVED2,
180 PERIPH_ID_V_RESERVED4,
193 PERIPH_ID_HDA2CODEC2X,
197 PERIPH_ID_V_RESERVED17,
198 PERIPH_ID_V_RESERVED18,
199 PERIPH_ID_V_RESERVED19,
200 PERIPH_ID_V_RESERVED20,
201 PERIPH_ID_V_RESERVED21,
202 PERIPH_ID_V_RESERVED22,
206 PERIPH_ID_EXTPERIPH1,
207 PERIPH_ID_EXTPERIPH2,
208 PERIPH_ID_EXTPERIPH3,
212 PERIPH_ID_V_RESERVED30,
213 PERIPH_ID_V_RESERVED31,
216 PERIPH_ID_HDA2HDMICODEC,
218 PERIPH_ID_W_RESERVED2,
219 PERIPH_ID_W_RESERVED3,
220 PERIPH_ID_W_RESERVED4,
221 PERIPH_ID_W_RESERVED5,
222 PERIPH_ID_W_RESERVED6,
223 PERIPH_ID_W_RESERVED7,
227 PERIPH_ID_W_RESERVED9,
228 PERIPH_ID_W_RESERVED10,
229 PERIPH_ID_W_RESERVED11,
230 PERIPH_ID_W_RESERVED12,
231 PERIPH_ID_W_RESERVED13,
232 PERIPH_ID_XUSB_PADCTL,
233 PERIPH_ID_W_RESERVED15,
236 PERIPH_ID_W_RESERVED16,
237 PERIPH_ID_W_RESERVED17,
238 PERIPH_ID_W_RESERVED18,
239 PERIPH_ID_W_RESERVED19,
240 PERIPH_ID_W_RESERVED20,
243 PERIPH_ID_W_RESERVED23,
251 PERIPH_ID_W_RESERVED29,
252 PERIPH_ID_W_RESERVED30,
253 PERIPH_ID_W_RESERVED31,
257 PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
258 PERIPH_ID_X_RESERVED1,
259 PERIPH_ID_X_RESERVED2,
260 PERIPH_ID_X_RESERVED3,
264 PERIPH_ID_X_RESERVED7,
267 PERIPH_ID_X_RESERVED8,
268 PERIPH_ID_X_RESERVED9,
269 PERIPH_ID_X_RESERVED10,
271 PERIPH_ID_X_RESERVED12,
272 PERIPH_ID_X_RESERVED13,
274 PERIPH_ID_X_RESERVED15,
277 PERIPH_ID_HDMI_AUDIO,
280 PERIPH_ID_X_RESERVED19,
284 PERIPH_ID_X_RESERVED23,
308 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
309 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
310 * confusion bewteen PERIPH_ID_... and PERIPHC_...
312 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
315 enum periphc_internal_id {
398 PERIPHC_40h = PERIPHC_VW_FIRST,
434 PERIPHC_HDA, /* 0x428 */
439 PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
442 PERIPHC_XUSB_CORE_DEV,
483 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
484 #define PERIPH_REG(id) \
485 (id < PERIPH_ID_VW_FIRST) ? \
486 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
488 /* Mask value for a clock (within PERIPH_REG(id)) */
489 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
491 /* return 1 if a PLL ID is in range */
492 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
494 /* return 1 if a peripheral ID is in range */
495 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
496 (id) < PERIPH_ID_COUNT)
498 #endif /* _TEGRA124_CLOCK_TABLES_H_ */