3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra124 clock PLL tables */
10 #ifndef _TEGRA124_CLOCK_TABLES_H_
11 #define _TEGRA124_CLOCK_TABLES_H_
13 /* The PLLs supported by the hardware */
16 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
23 /* now the simple ones */
24 CLOCK_ID_FIRST_SIMPLE,
25 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
29 /* These are the base clocks (inputs to the Tegra SoC) */
33 CLOCK_ID_COUNT, /* number of PLLs */
36 * These are clock IDs that are used in table clock_source[][]
37 * but will not be assigned as a clock source for any peripheral.
48 /* The clocks supported by the hardware */
52 /* Low word: 31:0 (DEVICES_L) */
53 PERIPH_ID_CPU = PERIPH_ID_FIRST,
92 /* Middle word: 63:32 (DEVICES_H) */
106 PERIPH_ID_RESERVED43,
114 PERIPH_ID_RESERVED49,
118 PERIPH_ID_RESERVED53,
127 PERIPH_ID_RESERVED60,
132 /* Upper word 95:64 (DEVICES_U) */
133 PERIPH_ID_RESERVED64,
148 PERIPH_ID_TRACECLKIN,
153 PERIPH_ID_RESERVED80,
157 PERIPH_ID_RESERVED84,
158 PERIPH_ID_RESERVED85,
159 PERIPH_ID_RESERVED86,
163 PERIPH_ID_RESERVED88,
165 PERIPH_ID_RESERVED90,
167 PERIPH_ID_RESERVED92,
168 PERIPH_ID_RESERVED93,
169 PERIPH_ID_RESERVED94,
174 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
176 PERIPH_ID_V_RESERVED2,
178 PERIPH_ID_V_RESERVED4,
191 PERIPH_ID_HDA2CODEC2X,
195 PERIPH_ID_V_RESERVED17,
196 PERIPH_ID_V_RESERVED18,
197 PERIPH_ID_V_RESERVED19,
198 PERIPH_ID_V_RESERVED20,
199 PERIPH_ID_V_RESERVED21,
200 PERIPH_ID_V_RESERVED22,
204 PERIPH_ID_EXTPERIPH1,
205 PERIPH_ID_EXTPERIPH2,
206 PERIPH_ID_EXTPERIPH3,
210 PERIPH_ID_V_RESERVED30,
211 PERIPH_ID_V_RESERVED31,
214 PERIPH_ID_HDA2HDMICODEC,
216 PERIPH_ID_W_RESERVED2,
217 PERIPH_ID_W_RESERVED3,
218 PERIPH_ID_W_RESERVED4,
219 PERIPH_ID_W_RESERVED5,
220 PERIPH_ID_W_RESERVED6,
221 PERIPH_ID_W_RESERVED7,
225 PERIPH_ID_W_RESERVED9,
226 PERIPH_ID_W_RESERVED10,
227 PERIPH_ID_W_RESERVED11,
228 PERIPH_ID_W_RESERVED12,
229 PERIPH_ID_W_RESERVED13,
230 PERIPH_ID_XUSB_PADCTL,
231 PERIPH_ID_W_RESERVED15,
234 PERIPH_ID_W_RESERVED16,
235 PERIPH_ID_W_RESERVED17,
236 PERIPH_ID_W_RESERVED18,
237 PERIPH_ID_W_RESERVED19,
238 PERIPH_ID_W_RESERVED20,
241 PERIPH_ID_W_RESERVED23,
249 PERIPH_ID_W_RESERVED29,
250 PERIPH_ID_W_RESERVED30,
251 PERIPH_ID_W_RESERVED31,
255 PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
256 PERIPH_ID_X_RESERVED1,
257 PERIPH_ID_X_RESERVED2,
258 PERIPH_ID_X_RESERVED3,
262 PERIPH_ID_X_RESERVED7,
265 PERIPH_ID_X_RESERVED8,
266 PERIPH_ID_X_RESERVED9,
267 PERIPH_ID_X_RESERVED10,
269 PERIPH_ID_X_RESERVED12,
270 PERIPH_ID_X_RESERVED13,
272 PERIPH_ID_X_RESERVED15,
275 PERIPH_ID_HDMI_AUDIO,
278 PERIPH_ID_X_RESERVED19,
282 PERIPH_ID_X_RESERVED23,
287 PERIPH_ID_X_RESERVED26,
288 PERIPH_ID_X_RESERVED27,
289 PERIPH_ID_X_RESERVED28,
290 PERIPH_ID_X_RESERVED29,
291 PERIPH_ID_X_RESERVED30,
292 PERIPH_ID_X_RESERVED31,
306 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
307 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
308 * confusion bewteen PERIPH_ID_... and PERIPHC_...
310 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
313 enum periphc_internal_id {
396 PERIPHC_40h = PERIPHC_VW_FIRST,
432 PERIPHC_HDA, /* 0x428 */
437 PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
440 PERIPHC_XUSB_CORE_DEV,
481 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
482 #define PERIPH_REG(id) \
483 (id < PERIPH_ID_VW_FIRST) ? \
484 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
486 /* Mask value for a clock (within PERIPH_REG(id)) */
487 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
489 /* return 1 if a PLL ID is in range */
490 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
492 /* return 1 if a peripheral ID is in range */
493 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
494 (id) < PERIPH_ID_COUNT)
496 #endif /* _TEGRA124_CLOCK_TABLES_H_ */