2 * (C) Copyright 2010-2013
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA124_FLOW_H_
9 #define _TEGRA124_FLOW_H_
12 u32 halt_cpu_events; /* offset 0x00 */
13 u32 halt_cop_events; /* offset 0x04 */
14 u32 cpu_csr; /* offset 0x08 */
15 u32 cop_csr; /* offset 0x0c */
16 u32 xrq_events; /* offset 0x10 */
17 u32 halt_cpu1_events; /* offset 0x14 */
18 u32 cpu1_csr; /* offset 0x18 */
19 u32 halt_cpu2_events; /* offset 0x1c */
20 u32 cpu2_csr; /* offset 0x20 */
21 u32 halt_cpu3_events; /* offset 0x24 */
22 u32 cpu3_csr; /* offset 0x28 */
23 u32 cluster_control; /* offset 0x2c */
24 u32 halt_cop1_events; /* offset 0x30 */
25 u32 halt_cop1_csr; /* offset 0x34 */
26 u32 cpu_pwr_csr; /* offset 0x38 */
27 u32 mpid; /* offset 0x3c */
28 u32 ram_repair; /* offset 0x40 */
29 u32 flow_dbg_sel; /* offset 0x44 */
30 u32 flow_dbg_cnt0; /* offset 0x48 */
31 u32 flow_dbg_cnt1; /* offset 0x4c */
32 u32 flow_dbg_qual; /* offset 0x50 */
33 u32 flow_ctlr_spare; /* offset 0x54 */
34 u32 ram_repair_cluster1;/* offset 0x58 */
37 /* HALT_COP_EVENTS_0, 0x04 */
38 #define EVENT_MSEC (1 << 24)
39 #define EVENT_USEC (1 << 25)
40 #define EVENT_JTAG (1 << 28)
41 #define EVENT_MODE_STOP (2 << 29)
43 /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
44 #define ACTIVE_LP (1 << 0)
47 #define CSR_ENABLE (1 << 0)
48 #define CSR_IMMEDIATE_WAKE (1 << 3)
49 #define CSR_WAIT_WFI_SHIFT 8
50 #define CSR_PWR_OFF_STS (1 << 16)
52 /* RAM_REPAIR, 0x40, 0x58 */
54 RAM_REPAIR_REQ = 0x1 << 0,
55 RAM_REPAIR_STS = 0x1 << 1,
58 #endif /* _TEGRA124_FLOW_H_ */