3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA124_PINMUX_H_
9 #define _TEGRA124_PINMUX_H_
12 * Pin groups which we adjust. There are three basic attributes of each pin
13 * group which use this enum:
17 * - tristate or normal
20 PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
44 PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
46 PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
49 PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
72 /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
73 PINGRP_GPIO_PC7, /* offset 0x31c0 */
108 PINGRP_GPIO_PI4, /* offset 0x324c */
121 PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
151 PINGRP_KB_COL0, /* offset 0x32fc */
160 PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
185 PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
191 PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
192 PINGRP_PEX_L0_CLKREQ,
194 PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
195 PINGRP_PEX_L1_CLKREQ,
196 PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
203 PINGRP_SDMMC3_CLK_LB_IN,
204 PINGRP_SDMMC3_CLK_LB_OUT,
207 PINGRP_KB_ROW16, /* offset 0x340c */
211 PINGRP_DP_HPD, /* last reg offset = 0x3430 */
216 PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
223 PDRIVE_PINGROUP_CDEV1,
224 PDRIVE_PINGROUP_CDEV2,
225 PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
226 PDRIVE_PINGROUP_DAP2,
227 PDRIVE_PINGROUP_DAP3,
228 PDRIVE_PINGROUP_DAP4,
230 PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
234 PDRIVE_PINGROUP_UART2,
235 PDRIVE_PINGROUP_UART3,
236 PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
237 PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
239 PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
245 PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
246 PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
247 PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
248 PDRIVE_PINGROUP_DAP5,
249 PDRIVE_PINGROUP_VBUS,
252 PDRIVE_PINGROUP_SDIO4,
254 PDRIVE_PINGROUP_COUNT,
258 * Functions which can be assigned to each of the pin groups. The values here
259 * bear no relation to the values programmed into pinmux registers and are
260 * purely a convenience. The translation is done through a table search.
265 PMUX_FUNC_AUDIO_SYNC,
274 PMUX_FUNC_EMC_TEST0_DLL,
275 PMUX_FUNC_EMC_TEST1_DLL,
320 PMUX_FUNC_VI_SENSOR_CLK,
322 /* End of Tegra2 MUX selectors */
335 PMUX_FUNC_EXTPERIPH1,
336 PMUX_FUNC_EXTPERIPH2,
337 PMUX_FUNC_EXTPERIPH3,
366 /* End of Tegra3 MUX selectors */
374 PMUX_FUNC_RESET_OUT_N,
375 /* End of Tegra114 MUX selectors */
379 PMUX_FUNC_INVALID = 0x4000,
380 PMUX_FUNC_RSVD1 = 0x8000,
381 PMUX_FUNC_RSVD2 = 0x8001,
382 PMUX_FUNC_RSVD3 = 0x8002,
383 PMUX_FUNC_RSVD4 = 0x8003,
386 /* return 1 if a pmux_func is in range */
387 #define pmux_func_isvalid(func) \
388 ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
389 (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
391 /* return 1 if a pingrp is in range */
392 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
394 /* The pullup/pulldown state of a pin group */
396 PMUX_PULL_NORMAL = 0,
400 /* return 1 if a pin_pupd_is in range */
401 #define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
402 ((pupd) <= PMUX_PULL_UP))
404 /* Defines whether a pin group is tristated or in normal operation */
407 PMUX_TRI_TRISTATE = 1,
409 /* return 1 if a pin_tristate_is in range */
410 #define pmux_pin_tristate_isvalid(tristate) \
411 (((tristate) >= PMUX_TRI_NORMAL) && \
412 ((tristate) <= PMUX_TRI_TRISTATE))
419 /* return 1 if a pin_io_is in range */
420 #define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
421 ((io) <= PMUX_PIN_INPUT))
424 PMUX_PIN_LOCK_DEFAULT = 0,
425 PMUX_PIN_LOCK_DISABLE,
426 PMUX_PIN_LOCK_ENABLE,
428 /* return 1 if a pin_lock is in range */
429 #define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
430 ((lock) <= PMUX_PIN_LOCK_ENABLE))
433 PMUX_PIN_OD_DEFAULT = 0,
437 /* return 1 if a pin_od is in range */
438 #define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
439 ((od) <= PMUX_PIN_OD_ENABLE))
441 enum pmux_pin_ioreset {
442 PMUX_PIN_IO_RESET_DEFAULT = 0,
443 PMUX_PIN_IO_RESET_DISABLE,
444 PMUX_PIN_IO_RESET_ENABLE,
446 /* return 1 if a pin_ioreset_is in range */
447 #define pmux_pin_ioreset_isvalid(ioreset) \
448 (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
449 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
451 enum pmux_pin_rcv_sel {
452 PMUX_PIN_RCV_SEL_DEFAULT = 0,
453 PMUX_PIN_RCV_SEL_NORMAL,
454 PMUX_PIN_RCV_SEL_HIGH,
456 /* return 1 if a pin_rcv_sel_is in range */
457 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
458 (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
459 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
461 /* Available power domains used by pin groups */
482 #define PGRP_SLWF_NONE -1
483 #define PGRP_SLWF_MAX 3
484 #define PGRP_SLWR_NONE PGRP_SLWF_NONE
485 #define PGRP_SLWR_MAX PGRP_SLWF_MAX
487 #define PGRP_DRVUP_NONE -1
488 #define PGRP_DRVUP_MAX 127
489 #define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
490 #define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
492 #define PGRP_SCHMT_NONE -1
493 #define PGRP_HSM_NONE PGRP_SCHMT_NONE
495 /* return 1 if a padgrp is in range */
496 #define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
498 /* return 1 if a slew-rate rising/falling edge value is in range */
499 #define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
500 (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
502 /* return 1 if a driver output pull-up/down strength code value is in range */
503 #define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
504 (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
506 /* return 1 if a low-power mode value is in range */
507 #define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
508 (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
510 /* Defines a pin group cfg's low-power mode select */
519 /* Defines whether a pin group cfg's schmidt is enabled or not */
521 PGRP_SCHMT_DISABLE = 0,
522 PGRP_SCHMT_ENABLE = 1,
525 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
527 PGRP_HSM_DISABLE = 0,
532 * This defines the configuration for a pin group's pad control config
534 struct padctrl_config {
535 enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
536 int slwf; /* falling edge slew */
537 int slwr; /* rising edge slew */
538 int drvup; /* pull-up drive strength */
539 int drvdn; /* pull-down drive strength */
540 enum pgrp_lpmd lpmd; /* low-power mode selection */
541 enum pgrp_schmt schmt; /* schmidt enable */
542 enum pgrp_hsm hsm; /* high-speed mode enable */
545 /* Tegra124 pin drive group and pin mux registers */
546 #define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
547 #define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
548 PDRIVE_PINGROUP_COUNT)
549 struct pmux_tri_ctlr {
550 uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */
551 uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
553 uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
555 uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
556 uint pmt_reserved5[PMUX_OFFSET];
557 uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
561 * This defines the configuration for a pin, including the function assigned,
562 * pull up/down settings and tristate settings. Having set up one of these
563 * you can call pinmux_config_pingroup() to configure a pin in one step. Also
564 * available is pinmux_config_table() to configure a list of pins.
566 struct pingroup_config {
567 enum pmux_pingrp pingroup; /* pin group PINGRP_... */
568 enum pmux_func func; /* function to assign FUNC_... */
569 enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
570 enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
571 enum pmux_pin_io io; /* input or output PMUX_PIN_... */
572 enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
573 enum pmux_pin_od od; /* open-drain or push-pull driver */
574 enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
575 enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
576 /* VIL/VIH receivers */
579 /* Set a pin group to tristate */
580 void pinmux_tristate_enable(enum pmux_pingrp pin);
582 /* Set a pin group to normal (non tristate) */
583 void pinmux_tristate_disable(enum pmux_pingrp pin);
585 /* Set the pull up/down feature for a pin group */
586 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
588 /* Set the mux function for a pin group */
589 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
591 /* Set the complete configuration for a pin group */
592 void pinmux_config_pingroup(struct pingroup_config *config);
594 /* Set a pin group to tristate or normal */
595 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
597 /* Set a pin group as input or output */
598 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
601 * Configure a list of pin groups
603 * @param config List of config items
604 * @param len Number of config items in list
606 void pinmux_config_table(struct pingroup_config *config, int len);
608 /* Set a group of pins from a table */
609 void pinmux_init(void);
612 * Set the GP pad configs
614 * @param config List of config items
615 * @param len Number of config items in list
617 void padgrp_config_table(struct padctrl_config *config, int len);
619 #endif /* _TEGRA124_PINMUX_H_ */