3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __ASM_ARCH_TEGRA_DISPLAY_H
9 #define __ASM_ARCH_TEGRA_DISPLAY_H
11 #include <asm/arch/dc.h>
14 /* This holds information about a window which can be displayed */
16 enum win_color_depth_id fmt; /* Color depth/format */
17 unsigned bpp; /* Bits per pixel */
18 phys_addr_t phys_addr; /* Physical address in memory */
19 unsigned x; /* Horizontal address offset (bytes) */
20 unsigned y; /* Veritical address offset (bytes) */
21 unsigned w; /* Width of source window */
22 unsigned h; /* Height of source window */
23 unsigned stride; /* Number of bytes per line */
24 unsigned out_x; /* Left edge of output window (col) */
25 unsigned out_y; /* Top edge of output window (row) */
26 unsigned out_w; /* Width of output window in pixels */
27 unsigned out_h; /* Height of output window in pixels */
30 #define FDT_LCD_TIMINGS 4
33 FDT_LCD_TIMING_REF_TO_SYNC,
34 FDT_LCD_TIMING_SYNC_WIDTH,
35 FDT_LCD_TIMING_BACK_PORCH,
36 FDT_LCD_TIMING_FRONT_PORCH,
42 FDT_LCD_CACHE_OFF = 0,
43 FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0,
44 FDT_LCD_CACHE_WRITE_BACK = 1 << 1,
45 FDT_LCD_CACHE_FLUSH = 1 << 2,
46 FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK |
50 /* Information about the display controller */
51 struct fdt_disp_config {
52 int valid; /* config is valid */
53 int width; /* width in pixels */
54 int height; /* height in pixels */
55 int bpp; /* number of bits per pixel */
58 * log2 of number of bpp, in general, unless it bpp is 24 in which
59 * case this field holds 24 also! This is a U-Boot thing.
62 struct disp_ctlr *disp; /* Display controller to use */
63 fdt_addr_t frame_buffer; /* Address of frame buffer */
64 unsigned pixel_clock; /* Pixel clock in Hz */
65 uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
66 uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
67 int panel_node; /* node offset of panel information */
70 /* Information about the LCD panel */
71 struct fdt_panel_config {
72 int pwm_channel; /* PWM channel to use for backlight */
73 enum lcd_cache_t cache_type;
75 struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */
76 struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */
77 struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */
78 struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */
80 * Panel required timings
81 * Timing 1: delay between panel_vdd-rise and data-rise
82 * Timing 2: delay between data-rise and backlight_vdd-rise
83 * Timing 3: delay between backlight_vdd and pwm-rise
84 * Timing 4: delay between pwm-rise and backlight_en-rise
86 uint panel_timings[FDT_LCD_TIMINGS];
90 * Register a new display based on device tree configuration.
92 * The frame buffer can be positioned by U-Boot or overriden by the fdt.
93 * You should pass in the U-Boot address here, and check the contents of
94 * struct fdt_disp_config to see what was actually chosen.
96 * @param blob Device tree blob
97 * @param default_lcd_base Default address of LCD frame buffer
98 * @return 0 if ok, -1 on error (unsupported bits per pixel)
100 int tegra_display_probe(const void *blob, void *default_lcd_base);
103 * Return the current display configuration
105 * @return pointer to display configuration, or NULL if there is no valid
108 struct fdt_disp_config *tegra_display_get_config(void);
111 * Perform the next stage of the LCD init if it is time to do so.
113 * LCD init can be time-consuming because of the number of delays we need
114 * while waiting for the backlight power supply, etc. This function can
115 * be called at various times during U-Boot operation to advance the
116 * initialization of the LCD to the next stage if sufficient time has
117 * passed since the last stage. It keeps track of what stage it is up to
118 * and the time that it is permitted to move to the next stage.
120 * The final call should have wait=1 to complete the init.
122 * @param blob fdt blob containing LCD information
123 * @param wait 1 to wait until all init is complete, and then return
124 * 0 to return immediately, potentially doing nothing if it is
125 * not yet time for the next init.
127 int tegra_lcd_check_next_stage(const void *blob, int wait);
130 * Set up the maximum LCD size so we can size the frame buffer.
132 * @param blob fdt blob containing LCD information
134 void tegra_lcd_early_init(const void *blob);
136 #endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/